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https://github.com/torvalds/linux
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a9ff696160
Making virt_to_pfn() a static inline taking a strongly typed (const void *) makes the contract of a passing a pointer of that type to the function explicit and exposes any misuse of the macro virt_to_pfn() acting polymorphic and accepting many types such as (void *), (unitptr_t) or (unsigned long) as arguments without warnings. Doing this is a bit intrusive: virt_to_pfn() requires PHYS_PFN_OFFSET and PAGE_SHIFT to be defined, and this is defined in <asm/page.h>, so this must be included *before* <asm/memory.h>. The use of macros were obscuring the unclear inclusion order here, as the macros would eventually be resolved, but a static inline like this cannot be compiled with unresolved macros. The naive solution to include <asm/page.h> at the top of <asm/memory.h> does not work, because <asm/memory.h> sometimes includes <asm/page.h> at the end of itself, which would create a confusing inclusion loop. So instead, take the approach to always unconditionally include <asm/page.h> at the end of <asm/memory.h> arch/arm uses <asm/memory.h> explicitly in a lot of places, however it turns out that if we just unconditionally include <asm/memory.h> into <asm/page.h> and switch all inclusions of <asm/memory.h> to <asm/page.h> instead, we enforce the right order and <asm/memory.h> will always have access to the definitions. Put an inclusion guard in place making it impossible to include <asm/memory.h> explicitly. Link: https://lore.kernel.org/linux-mm/20220701160004.2ffff4e5ab59a55499f4c736@linux-foundation.org/ Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
65 lines
1.4 KiB
ArmAsm
65 lines
1.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Tony Xie <tony.xie@rock-chips.com>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/page.h>
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.data
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/*
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* this code will be copied from
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* ddr to sram for system resumeing.
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* so it is ".data section".
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*/
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.align 2
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ENTRY(rockchip_slp_cpu_resume)
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
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mrc p15, 0, r1, c0, c0, 5
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and r1, r1, #0xf
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cmp r1, #0
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/* olny cpu0 can continue to run, the others is halt here */
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beq cpu0run
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secondary_loop:
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wfe
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b secondary_loop
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cpu0run:
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ldr r3, rkpm_bootdata_l2ctlr_f
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cmp r3, #0
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beq sp_set
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ldr r3, rkpm_bootdata_l2ctlr
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mcr p15, 1, r3, c9, c0, 2
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sp_set:
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ldr sp, rkpm_bootdata_cpusp
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ldr r1, rkpm_bootdata_cpu_code
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bx r1
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ENDPROC(rockchip_slp_cpu_resume)
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/* Parameters filled in by the kernel */
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/* Flag for whether to restore L2CTLR on resume */
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.global rkpm_bootdata_l2ctlr_f
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rkpm_bootdata_l2ctlr_f:
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.long 0
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/* Saved L2CTLR to restore on resume */
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.global rkpm_bootdata_l2ctlr
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rkpm_bootdata_l2ctlr:
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.long 0
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/* CPU resume SP addr */
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.globl rkpm_bootdata_cpusp
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rkpm_bootdata_cpusp:
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.long 0
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/* CPU resume function (physical address) */
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.globl rkpm_bootdata_cpu_code
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rkpm_bootdata_cpu_code:
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.long 0
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ENTRY(rk3288_bootram_sz)
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.word . - rockchip_slp_cpu_resume
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