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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
210 lines
6.5 KiB
C
210 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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#ifndef __SOUND_WM8776_H
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#define __SOUND_WM8776_H
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/*
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* ALSA driver for ICEnsemble VT17xx
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*
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* Lowlevel functions for WM8776 codec
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*
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* Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
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*/
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#define WM8776_REG_HPLVOL 0x00
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#define WM8776_REG_HPRVOL 0x01
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#define WM8776_REG_HPMASTER 0x02
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#define WM8776_HPVOL_MASK 0x17f /* incl. update bit */
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#define WM8776_VOL_HPZCEN (1 << 7) /* zero cross detect */
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#define WM8776_VOL_UPDATE (1 << 8) /* update volume */
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#define WM8776_REG_DACLVOL 0x03
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#define WM8776_REG_DACRVOL 0x04
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#define WM8776_REG_DACMASTER 0x05
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#define WM8776_DACVOL_MASK 0x1ff /* incl. update bit */
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#define WM8776_REG_PHASESWAP 0x06
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#define WM8776_PHASE_INVERTL (1 << 0)
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#define WM8776_PHASE_INVERTR (1 << 1)
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#define WM8776_REG_DACCTRL1 0x07
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#define WM8776_DAC_DZCEN (1 << 0)
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#define WM8776_DAC_ATC (1 << 1)
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#define WM8776_DAC_IZD (1 << 2)
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#define WM8776_DAC_TOD (1 << 3)
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#define WM8776_DAC_PL_MASK 0xf0
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#define WM8776_DAC_PL_LL (1 << 4) /* L chan: L signal */
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#define WM8776_DAC_PL_LR (2 << 4) /* L chan: R signal */
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#define WM8776_DAC_PL_LB (3 << 4) /* L chan: both */
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#define WM8776_DAC_PL_RL (1 << 6) /* R chan: L signal */
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#define WM8776_DAC_PL_RR (2 << 6) /* R chan: R signal */
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#define WM8776_DAC_PL_RB (3 << 6) /* R chan: both */
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#define WM8776_REG_DACMUTE 0x08
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#define WM8776_DACMUTE (1 << 0)
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#define WM8776_REG_DACCTRL2 0x09
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#define WM8776_DAC2_DEEMPH (1 << 0)
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#define WM8776_DAC2_ZFLAG_DISABLE (0 << 1)
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#define WM8776_DAC2_ZFLAG_OWN (1 << 1)
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#define WM8776_DAC2_ZFLAG_BOTH (2 << 1)
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#define WM8776_DAC2_ZFLAG_EITHER (3 << 1)
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#define WM8776_REG_DACIFCTRL 0x0a
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#define WM8776_FMT_RIGHTJ (0 << 0)
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#define WM8776_FMT_LEFTJ (1 << 0)
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#define WM8776_FMT_I2S (2 << 0)
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#define WM8776_FMT_DSP (3 << 0)
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#define WM8776_FMT_DSP_LATE (1 << 2) /* in DSP mode */
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#define WM8776_FMT_LRC_INVERTED (1 << 2) /* in other modes */
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#define WM8776_FMT_BCLK_INVERTED (1 << 3)
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#define WM8776_FMT_16BIT (0 << 4)
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#define WM8776_FMT_20BIT (1 << 4)
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#define WM8776_FMT_24BIT (2 << 4)
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#define WM8776_FMT_32BIT (3 << 4)
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#define WM8776_REG_ADCIFCTRL 0x0b
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#define WM8776_FMT_ADCMCLK_INVERTED (1 << 6)
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#define WM8776_FMT_ADCHPD (1 << 8)
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#define WM8776_REG_MSTRCTRL 0x0c
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#define WM8776_IF_ADC256FS (2 << 0)
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#define WM8776_IF_ADC384FS (3 << 0)
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#define WM8776_IF_ADC512FS (4 << 0)
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#define WM8776_IF_ADC768FS (5 << 0)
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#define WM8776_IF_OVERSAMP64 (1 << 3)
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#define WM8776_IF_DAC128FS (0 << 4)
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#define WM8776_IF_DAC192FS (1 << 4)
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#define WM8776_IF_DAC256FS (2 << 4)
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#define WM8776_IF_DAC384FS (3 << 4)
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#define WM8776_IF_DAC512FS (4 << 4)
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#define WM8776_IF_DAC768FS (5 << 4)
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#define WM8776_IF_DAC_MASTER (1 << 7)
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#define WM8776_IF_ADC_MASTER (1 << 8)
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#define WM8776_REG_PWRDOWN 0x0d
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#define WM8776_PWR_PDWN (1 << 0)
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#define WM8776_PWR_ADCPD (1 << 1)
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#define WM8776_PWR_DACPD (1 << 2)
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#define WM8776_PWR_HPPD (1 << 3)
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#define WM8776_PWR_AINPD (1 << 6)
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#define WM8776_REG_ADCLVOL 0x0e
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#define WM8776_REG_ADCRVOL 0x0f
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#define WM8776_ADC_GAIN_MASK 0xff
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#define WM8776_ADC_ZCEN (1 << 8)
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#define WM8776_REG_ALCCTRL1 0x10
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#define WM8776_ALC1_LCT_MASK 0x0f /* 0=-16dB, 1=-15dB..15=-1dB */
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#define WM8776_ALC1_MAXGAIN_MASK 0x70 /* 0,1=0dB, 2=+4dB...7=+24dB */
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#define WM8776_ALC1_LCSEL_MASK 0x180
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#define WM8776_ALC1_LCSEL_LIMITER (0 << 7)
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#define WM8776_ALC1_LCSEL_ALCR (1 << 7)
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#define WM8776_ALC1_LCSEL_ALCL (2 << 7)
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#define WM8776_ALC1_LCSEL_ALCSTEREO (3 << 7)
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#define WM8776_REG_ALCCTRL2 0x11
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#define WM8776_ALC2_HOLD_MASK 0x0f /*0=0ms, 1=2.67ms, 2=5.33ms.. */
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#define WM8776_ALC2_ZCEN (1 << 7)
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#define WM8776_ALC2_LCEN (1 << 8)
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#define WM8776_REG_ALCCTRL3 0x12
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#define WM8776_ALC3_ATK_MASK 0x0f
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#define WM8776_ALC3_DCY_MASK 0xf0
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#define WM8776_ALC3_FDECAY (1 << 8)
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#define WM8776_REG_NOISEGATE 0x13
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#define WM8776_NGAT_ENABLE (1 << 0)
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#define WM8776_NGAT_THR_MASK 0x1c /*0=-78dB, 1=-72dB...7=-36dB */
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#define WM8776_REG_LIMITER 0x14
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#define WM8776_LIM_MAXATTEN_MASK 0x0f
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#define WM8776_LIM_TRANWIN_MASK 0x70 /*0=0us, 1=62.5us, 2=125us.. */
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#define WM8776_REG_ADCMUX 0x15
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#define WM8776_ADC_MUX_AIN1 (1 << 0)
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#define WM8776_ADC_MUX_AIN2 (1 << 1)
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#define WM8776_ADC_MUX_AIN3 (1 << 2)
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#define WM8776_ADC_MUX_AIN4 (1 << 3)
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#define WM8776_ADC_MUX_AIN5 (1 << 4)
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#define WM8776_ADC_MUTER (1 << 6)
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#define WM8776_ADC_MUTEL (1 << 7)
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#define WM8776_ADC_LRBOTH (1 << 8)
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#define WM8776_REG_OUTMUX 0x16
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#define WM8776_OUTMUX_DAC (1 << 0)
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#define WM8776_OUTMUX_AUX (1 << 1)
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#define WM8776_OUTMUX_BYPASS (1 << 2)
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#define WM8776_REG_RESET 0x17
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#define WM8776_REG_COUNT 0x17 /* don't cache the RESET register */
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struct snd_wm8776;
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struct snd_wm8776_ops {
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void (*write)(struct snd_wm8776 *wm, u8 addr, u8 data);
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};
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enum snd_wm8776_ctl_id {
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WM8776_CTL_DAC_VOL,
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WM8776_CTL_DAC_SW,
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WM8776_CTL_DAC_ZC_SW,
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WM8776_CTL_HP_VOL,
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WM8776_CTL_HP_SW,
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WM8776_CTL_HP_ZC_SW,
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WM8776_CTL_AUX_SW,
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WM8776_CTL_BYPASS_SW,
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WM8776_CTL_DAC_IZD_SW,
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WM8776_CTL_PHASE_SW,
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WM8776_CTL_DEEMPH_SW,
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WM8776_CTL_ADC_VOL,
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WM8776_CTL_ADC_SW,
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WM8776_CTL_INPUT1_SW,
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WM8776_CTL_INPUT2_SW,
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WM8776_CTL_INPUT3_SW,
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WM8776_CTL_INPUT4_SW,
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WM8776_CTL_INPUT5_SW,
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WM8776_CTL_AGC_SEL,
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WM8776_CTL_LIM_THR,
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WM8776_CTL_LIM_ATK,
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WM8776_CTL_LIM_DCY,
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WM8776_CTL_LIM_TRANWIN,
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WM8776_CTL_LIM_MAXATTN,
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WM8776_CTL_ALC_TGT,
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WM8776_CTL_ALC_ATK,
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WM8776_CTL_ALC_DCY,
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WM8776_CTL_ALC_MAXGAIN,
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WM8776_CTL_ALC_MAXATTN,
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WM8776_CTL_ALC_HLD,
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WM8776_CTL_NGT_SW,
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WM8776_CTL_NGT_THR,
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WM8776_CTL_COUNT,
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};
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#define WM8776_ENUM_MAX 16
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#define WM8776_FLAG_STEREO (1 << 0)
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#define WM8776_FLAG_VOL_UPDATE (1 << 1)
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#define WM8776_FLAG_INVERT (1 << 2)
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#define WM8776_FLAG_LIM (1 << 3)
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#define WM8776_FLAG_ALC (1 << 4)
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struct snd_wm8776_ctl {
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const char *name;
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snd_ctl_elem_type_t type;
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const char *const enum_names[WM8776_ENUM_MAX];
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const unsigned int *tlv;
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u16 reg1, reg2, mask1, mask2, min, max, flags;
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void (*set)(struct snd_wm8776 *wm, u16 ch1, u16 ch2);
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void (*get)(struct snd_wm8776 *wm, u16 *ch1, u16 *ch2);
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};
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enum snd_wm8776_agc_mode {
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WM8776_AGC_OFF,
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WM8776_AGC_LIM,
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WM8776_AGC_ALC_R,
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WM8776_AGC_ALC_L,
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WM8776_AGC_ALC_STEREO
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};
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struct snd_wm8776 {
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struct snd_card *card;
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struct snd_wm8776_ctl ctl[WM8776_CTL_COUNT];
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enum snd_wm8776_agc_mode agc_mode;
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struct snd_wm8776_ops ops;
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u16 regs[WM8776_REG_COUNT]; /* 9-bit registers */
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};
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void snd_wm8776_init(struct snd_wm8776 *wm);
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void snd_wm8776_resume(struct snd_wm8776 *wm);
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void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power);
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void snd_wm8776_volume_restore(struct snd_wm8776 *wm);
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int snd_wm8776_build_controls(struct snd_wm8776 *wm);
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#endif /* __SOUND_WM8776_H */
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