linux/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
Arnd Bergmann d5a51af940 mxs device tree changes for 3.11:
* A couple of new board support, cfa10055 and cfa10057
 * A few updates on cfa10036 device tree source
 * Some auart pinctrl data addition
 * Adopt soc bus infrastructure for mach-mxs
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Merge tag 'mxs-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt

From Shawn Guo:

mxs device tree changes for 3.11:

* A couple of new board support, cfa10055 and cfa10057
* A few updates on cfa10036 device tree source
* Some auart pinctrl data addition
* Adopt soc bus infrastructure for mach-mxs

* tag 'mxs-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6:
  ARM: mxs: dt: Add Crystalfontz CFA-10057 device tree
  ARM: mxs: dt: Add the Crystalfontz CFA-10055 device tree
  ARM: cfa10049: Switch the chip select pin of the LCD controller
  ARM: cfa10036: Add USB0 OTG port
  ARM: dts: apf28dev: Add touchscreen support for APF28dev
  ARM: mxs: Fix UARTs on M28EVK
  ARM: cfa10036: dt: Change i2c0 clock frequency
  ARM: dts: cfa10036: Change the OLED display to SSD1306
  ARM: mx28: add auart4 2 pins pinmux to imx28.dtsi
  ARM: mx28: add auart3 2 pins pinmux to imx28.dtsi
  ARM: mx28: add auart2 2 pins pinmux to imx28.dtsi
  ARM: mxs: Use soc bus infrastructure
  ARM: dts: mx28: Adjust the digctl compatible string
  ARM: mxs: Remove init_irq declaration in machine description

Includes an update to 3.10-rc6

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2013-06-20 02:06:36 +02:00

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/*
* Device Tree file for OpenBlocks AX3-4 board
*
* Copyright (C) 2012 Marvell
*
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
/include/ "armada-xp-mv78260.dtsi"
/ {
model = "PlatHome OpenBlocks AX3-4 board";
compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
chosen {
bootargs = "console=ttyS0,115200 earlyprintk";
};
memory {
device_type = "memory";
reg = <0 0x00000000 0 0xC0000000>; /* 3 GB */
};
soc {
ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */
0xe0000000 0 0xe0000000 0x8100000 /* PCIe */
0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>;
internal-regs {
serial@12000 {
clock-frequency = <250000000>;
status = "okay";
};
serial@12100 {
clock-frequency = <250000000>;
status = "okay";
};
pinctrl {
led_pins: led-pins-0 {
marvell,pins = "mpp49", "mpp51", "mpp53";
marvell,function = "gpio";
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&led_pins>;
red_led {
label = "red_led";
gpios = <&gpio1 17 1>;
default-state = "off";
};
yellow_led {
label = "yellow_led";
gpios = <&gpio1 19 1>;
default-state = "off";
};
green_led {
label = "green_led";
gpios = <&gpio1 21 1>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
};
gpio_keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@1 {
label = "Init Button";
linux,code = <116>;
gpios = <&gpio1 28 0>;
};
};
mdio {
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
phy3: ethernet-phy@3 {
reg = <3>;
};
};
ethernet@70000 {
status = "okay";
phy = <&phy0>;
phy-mode = "sgmii";
};
ethernet@74000 {
status = "okay";
phy = <&phy1>;
phy-mode = "sgmii";
};
ethernet@30000 {
status = "okay";
phy = <&phy2>;
phy-mode = "sgmii";
};
ethernet@34000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
i2c@11000 {
status = "okay";
clock-frequency = <400000>;
};
i2c@11100 {
status = "okay";
clock-frequency = <400000>;
s35390a: s35390a@30 {
compatible = "s35390a";
reg = <0x30>;
};
};
sata@a0000 {
nr-ports = <2>;
status = "okay";
};
/* Front side USB 0 */
usb@50000 {
status = "okay";
};
/* Front side USB 1 */
usb@51000 {
status = "okay";
};
/* USB interface in the mini-PCIe connector */
usb@52000 {
status = "okay";
};
devbus-bootcs@10400 {
status = "okay";
ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
/* Device Bus parameters are required */
/* Read parameters */
devbus,bus-width = <8>;
devbus,turn-off-ps = <60000>;
devbus,badr-skew-ps = <0>;
devbus,acc-first-ps = <124000>;
devbus,acc-next-ps = <248000>;
devbus,rd-setup-ps = <0>;
devbus,rd-hold-ps = <0>;
/* Write parameters */
devbus,sync-enable = <0>;
devbus,wr-high-ps = <60000>;
devbus,wr-low-ps = <60000>;
devbus,ale-wr-ps = <60000>;
/* NOR 128 MiB */
nor@0 {
compatible = "cfi-flash";
reg = <0 0x8000000>;
bank-width = <2>;
};
};
pcie-controller {
status = "okay";
/* Internal mini-PCIe connector */
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
};
};
};
};