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linux/arch/riscv/boot
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Emil Renner Berthing d4b95c445c riscv: dts: starfive: Add JH7100 cache controller 
The StarFive JH7100 SoC also features the SiFive L2 cache controller,
so add the device tree nodes for it.

Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-12-13 15:50:23 +00:00
..
dts riscv: dts: starfive: Add JH7100 cache controller 2023-12-13 15:50:23 +00:00
.gitignore riscv: efi: enable generic EFI compressed boot 2022-09-20 09:50:30 +02:00
install.sh kbuild: factor out the common installation code into scripts/install.sh 2022-05-11 21:45:53 +09:00
loader.lds.S riscv: Move kernel mapping outside of linear mapping 2021-04-26 08:25:04 -07:00
loader.S riscv: provide a flat image loader 2019-11-17 15:17:39 -08:00
Makefile riscv: boot: Fix creation of loader.bin 2023-11-06 09:39:26 -08:00