Palmer Dabbelt d26c4bbf99 RISC-V: SMP cleanup and new features ... This patch series now has evolved to contain several related changes. 1. Updated the assorted cleanup series by Palmer. The original cleanup patch series can be found here. http://lists.infradead.org/pipermail/linux-riscv/2018-August/001232.html 2. Implemented decoupling linux logical CPU ids from hart id. Some of the work has been inspired from ARM64. Tested on QEMU & HighFive Unleashed board with/without SMP enabled. 3. Included Anup's cleanup and IPI stat patch. All the patch series have been combined to avoid conflicts as a lot of common code is changed different patch sets. Atish has mostly addressed review comments and fixed checkpatch errors from Palmer's and Anup's series. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2018-10-22 17:41:43 -07:00
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configs	irqchip: add a SiFive PLIC driver	2018-08-13 08:31:32 -07:00
include	RISC-V: SMP cleanup and new features	2018-10-22 17:41:43 -07:00
kernel	RISC-V: SMP cleanup and new features	2018-10-22 17:41:43 -07:00
lib	RISC-V: Build tishift only on 64-bit	2018-10-22 17:02:55 -07:00
mm	RISC-V: Avoid corrupting the upper 32-bit of phys_addr_t in ioremap	2018-10-22 17:02:56 -07:00
Kconfig	RISC-V: Fix some RV32 bugs and build failures	2018-10-22 17:39:08 -07:00
Kconfig.debug	RISC-V: Cosmetic menuconfig changes	2018-10-22 17:38:20 -07:00
Makefile	riscv: Add support to no-FPU systems	2018-10-22 17:38:26 -07:00