Vineet Gupta cfd9d70a85 ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg ... ARC700 exception (and intr handling) didn't have auto stack switching thus had to rely on stashing a reg temporarily (to free it up) at a known place in memory, allowing to code up the low level stack switching. This however was not re-entrant in SMP which thus had to repurpose the per-cpu MMU SCRATCH DATA register otherwise used to "cache" the task pdg pointer (vs. reading it from mm struct) The newer HS cores do have auto-stack switching and thus even SMP builds can use the MMU SCRATCH reg as originally intended. This patch fixes the restriction to ARC700 SMP builds only Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2019-10-28 12:12:31 -07:00
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cache.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
dma.c	dma-mapping updates for 5.4:	2019-09-19 13:27:23 -07:00
extable.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
fault.c	ARC updates for 5.3-rc1	2019-07-16 15:07:51 -07:00
highmem.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
init.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
ioremap.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
Makefile	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
mmap.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
tlb.c	ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg	2019-10-28 12:12:31 -07:00
tlbex.S	ARCv2: mm: TLB Miss optim: SMP builds can cache pgd pointer in mmu scratch reg	2019-10-28 12:12:31 -07:00