linux/drivers/clk/meson/clk-pll.h
Neil Armstrong 39b8500283 clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL
The Meson G12A PCIE PLL is fined tuned to deliver a very precise
100MHz reference clock for the PCIe Analog PHY, and thus requires
a strict register sequence to enable the PLL.
To simplify, use the _init() op to enable the PLL and keep
the other ops except set_rate since the rate is fixed.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lkml.kernel.org/r/20190307141455.23879-2-narmstrong@baylibre.com
2019-04-01 10:45:11 +02:00

51 lines
993 B
C

/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2019 BayLibre, SAS.
* Author: Jerome Brunet <jbrunet@baylibre.com>
*/
#ifndef __MESON_CLK_PLL_H
#define __MESON_CLK_PLL_H
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include "parm.h"
struct pll_params_table {
unsigned int m;
unsigned int n;
};
struct pll_mult_range {
unsigned int min;
unsigned int max;
};
#define PLL_PARAMS(_m, _n) \
{ \
.m = (_m), \
.n = (_n), \
}
#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
struct meson_clk_pll_data {
struct parm en;
struct parm m;
struct parm n;
struct parm frac;
struct parm l;
struct parm rst;
const struct reg_sequence *init_regs;
unsigned int init_count;
const struct pll_params_table *table;
const struct pll_mult_range *range;
u8 flags;
};
extern const struct clk_ops meson_clk_pll_ro_ops;
extern const struct clk_ops meson_clk_pll_ops;
extern const struct clk_ops meson_clk_pcie_pll_ops;
#endif /* __MESON_CLK_PLL_H */