mirror of
https://github.com/torvalds/linux
synced 2024-10-09 12:54:52 +00:00
9209fb5189
The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management. It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.
Move the file to drivers/soc and add a Kconfig option for it, as well
as the whole drivers/soc boilerplate for CONFIG_SOC_SIFIVE.
Fixes: a967a289f1 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs")
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Borislav Petkov <bp@suse.de>
[paul.walmsley@sifive.com: keep the MAINTAINERS change specific to the L2$ controller code]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
31 lines
850 B
Makefile
31 lines
850 B
Makefile
# SPDX-License-Identifier: GPL-2.0
|
|
#
|
|
# Makefile for the Linux Kernel SOC specific device drivers.
|
|
#
|
|
|
|
obj-$(CONFIG_ARCH_ACTIONS) += actions/
|
|
obj-$(CONFIG_SOC_ASPEED) += aspeed/
|
|
obj-$(CONFIG_ARCH_AT91) += atmel/
|
|
obj-y += bcm/
|
|
obj-$(CONFIG_ARCH_DOVE) += dove/
|
|
obj-$(CONFIG_MACH_DOVE) += dove/
|
|
obj-y += fsl/
|
|
obj-$(CONFIG_ARCH_GEMINI) += gemini/
|
|
obj-$(CONFIG_ARCH_MXC) += imx/
|
|
obj-$(CONFIG_ARCH_IXP4XX) += ixp4xx/
|
|
obj-$(CONFIG_SOC_XWAY) += lantiq/
|
|
obj-y += mediatek/
|
|
obj-y += amlogic/
|
|
obj-y += qcom/
|
|
obj-y += renesas/
|
|
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
|
|
obj-$(CONFIG_SOC_SAMSUNG) += samsung/
|
|
obj-$(CONFIG_SOC_SIFIVE) += sifive/
|
|
obj-y += sunxi/
|
|
obj-$(CONFIG_ARCH_TEGRA) += tegra/
|
|
obj-y += ti/
|
|
obj-$(CONFIG_ARCH_U8500) += ux500/
|
|
obj-$(CONFIG_PLAT_VERSATILE) += versatile/
|
|
obj-y += xilinx/
|
|
obj-$(CONFIG_ARCH_ZX) += zte/
|