Greg Kroah-Hartman 50f737ab96 phy: for 5.6 ... *) Add support in PHY core to create link between PHY consumer and PHY provider *) Add DisplayPort PHY configuration set to be used for negotiating the configurations to be used between DisplayPort controller and DisplayPort PHY *) Add PHY wrapper driver (configure inputs to Cadence Sierra PHY) for TI's J721E SoC and adapt Cadence Sierra PHY driver to be used for J721E SoC (Supports USB and PCIe) *) Add PHY driver for eMMC PHY in Intel LGM SoC *) Add PHY support for 7216 and 7211 Broadcom SoCs which uses the new Synopsys USB Controller *) Add support for 16nm SATA PHY present in Broadcom 7216 SoC *) Fix lost packet issue, fix MDIO from getting inaccessible, fix occasional transaction failures, fix USB driver from crashing in Broadcom USB PHY driver *) Fix missing PCS SW reset in UFS PHY of Qualcomm SM8150 *) Use "struct phy_configure_opts_mipi_dphy" to pass parameters from display controller to rockchip-inno-dsidphy *) Other cleanups including compile testing for some of the PHY drivers, fixing Kconfig indentation, duplicate writes in drivers etc., Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> -----BEGIN PGP SIGNATURE----- iQJCBAABCgAsFiEEUXMr/TfP2p4suIY5Dlx4XIBNgtkFAl4hRU4OHGtpc2hvbkB0 aS5jb20ACgkQDlx4XIBNgtkSnw//a1zdT1NF2RApEAbSUcB+KHpckRLjKix4Q34r XexDI7/qVT1FQIDSOjxNOBhPVpATCE8O/pd71gVPUYqy67xmXhLK/FmBm90pzDYb JEt6zwaDoUaljFXN3OqXC1Z6q2hwRuKdERLQ0dajh8GAbkt0OOlzT8QXwv3m0YFg gUto2yytH8ZM/kdm3so1vc6vKtinW8QLlcigsgpaXVjQijeTaC5Wi1vxwgYeQE8K mHjipnCUl8mcuwKxAVFobSHxxSANWt6KJC0MOEB38xhsvylYgbE6ERoCHL5bERJA bsOJdiMAc3+UzlnbGlRNVTTkBReYWtSZ7MyHtjnPAl5xIpDk6/arPkX+KGzKTP/a MTC0XPHDXs2je+Nz2U2BRPecpjUkEDJ4rN1C8ZiqW6mJslsHmLE/NSax0uT9jX7V VK9Z6GJ2b7Yl/myf4DVyD6amN4EA8jK0U2q5tb3zI7boZG0RHauAfcStn1lKPBQV oBycIDPkcEbwOHRBimB3VIXJYcnVR0xEqiReU79tN2JZKKirlmkPmRfMVx2pS0Vc 5EvYigzVo0u0cC+Y7aEHpi4prEWaG+xw/6Y8l5QQ+BL4rJbNoL1281HT0m/v5YT2 x+N1uSDhc5vtRXGcSMadHl7DLDO9Wxh8WpI9bZ9aRvyy9xiUwAG/vaXSpoUIyOrH GRKuXXc= =76zg -----END PGP SIGNATURE----- Merge tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 5.6 *) Add support in PHY core to create link between PHY consumer and PHY provider *) Add DisplayPort PHY configuration set to be used for negotiating the configurations to be used between DisplayPort controller and DisplayPort PHY *) Add PHY wrapper driver (configure inputs to Cadence Sierra PHY) for TI's J721E SoC and adapt Cadence Sierra PHY driver to be used for J721E SoC (Supports USB and PCIe) *) Add PHY driver for eMMC PHY in Intel LGM SoC *) Add PHY support for 7216 and 7211 Broadcom SoCs which uses the new Synopsys USB Controller *) Add support for 16nm SATA PHY present in Broadcom 7216 SoC *) Fix lost packet issue, fix MDIO from getting inaccessible, fix occasional transaction failures, fix USB driver from crashing in Broadcom USB PHY driver *) Fix missing PCS SW reset in UFS PHY of Qualcomm SM8150 *) Use "struct phy_configure_opts_mipi_dphy" to pass parameters from display controller to rockchip-inno-dsidphy *) Other cleanups including compile testing for some of the PHY drivers, fixing Kconfig indentation, duplicate writes in drivers etc., Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> * tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (54 commits) dt-bindings: phy: Add PHY_TYPE_DP definition phy: ti: j721e-wiz: Fix return value check in wiz_probe() dt-bindings: usb: Convert Allwinner A80 USB PHY controller to a schema phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSE phy: ti: j721e-wiz: Manage typec-gpio-dir dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: cadence: Sierra: add phy_reset hook phy: cadence: Sierra: remove redundant initialization of pointer regmap phy: Add DisplayPort configuration options phy: Enable compile testing for some of drivers phy: mediatek: Fix Kconfig indentation phy: intel-lgm-emmc: Add support for eMMC PHY dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC dt-bindings: phy: Document WIZ (SERDES wrapper) bindings phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 phy: cadence: Sierra: Check for PLL lock during PHY power on phy: cadence: Sierra: Get reset control "array" for each link ...		2020-01-17 07:52:26 +01:00
..
Kconfig	phy/rockchip: inno-dsidphy: generalize parameter handling	2020-01-08 12:58:06 +05:30
Makefile	phy/rockchip: Add support for Innosilicon MIPI/LVDS/TTL PHY	2019-10-31 16:54:00 +05:30
phy-rockchip-dp.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 178	2019-05-30 11:29:19 -07:00
phy-rockchip-emmc.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 235	2019-06-19 17:09:07 +02:00
phy-rockchip-inno-dsidphy.c	phy/rockchip: inno-dsidphy: generalize parameter handling	2020-01-08 12:58:06 +05:30
phy-rockchip-inno-hdmi.c	phy/rockchip: inno-hdmi: round clock rate down to closest 1000 Hz	2019-12-31 15:46:08 +05:30
phy-rockchip-inno-usb2.c	phy: phy-rockchip-inno-usb2: add phy description for px30	2019-10-31 18:27:47 +05:30
phy-rockchip-pcie.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 235	2019-06-19 17:09:07 +02:00
phy-rockchip-typec.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 282	2019-06-05 17:36:37 +02:00
phy-rockchip-usb.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 235	2019-06-19 17:09:07 +02:00