mirror of
https://github.com/torvalds/linux
synced 2024-10-09 12:54:52 +00:00
dabedfede3
- Make gpio gate clks propagate rate setting up to parent * clk-gpio-flags: clk: clk-gpio: propagate rate change to parent * clk-tegra: (23 commits) clk: tegra: Use match_string() helper to simplify the code clk: tegra: Fix build error without CONFIG_PM_SLEEP clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP clk: tegra: Optimize PLLX restore on Tegra20/30 clk: tegra: Add suspend and resume support on Tegra210 clk: tegra: Share clk and rst register defines with Tegra clock driver clk: tegra: Use fence_udelay() during PLLU init clk: tegra: clk-dfll: Add suspend and resume support clk: tegra: clk-super: Add restore-context support clk: tegra: clk-super: Fix to enable PLLP branches to CPU clk: tegra: periph: Add restore_context support clk: tegra: Support for OSC context save and restore clk: tegra: pll: Save and restore pll context clk: tegra: pllout: Save and restore pllout context clk: tegra: divider: Save and restore divider rate clk: tegra: Reimplement SOR clocks on Tegra210 clk: tegra: Reimplement SOR clock on Tegra124 clk: tegra: Rename sor0_lvds to sor0_out clk: tegra: Move SOR0 implementation to Tegra124 clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC ... * clk-rockchip: clk: rockchip: protect the pclk_usb_grf as critical on px30 clk: rockchip: add video-related niu clocks as critical on px30 clk: rockchip: move px30 critical clocks to correct clock controller clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc clk: rockchip: make clk_half_divider_ops static * clk-sprd: clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle() * clk-pxa: clk: pxa: fix one of the pxa RTC clocks
101 lines
2.1 KiB
C
101 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0
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//
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// Spreadtrum clock infrastructure
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//
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// Copyright (C) 2017 Spreadtrum, Inc.
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// Author: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/regmap.h>
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#include "common.h"
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static const struct regmap_config sprdclk_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xffff,
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.fast_io = true,
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};
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static void sprd_clk_set_regmap(const struct sprd_clk_desc *desc,
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struct regmap *regmap)
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{
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int i;
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struct sprd_clk_common *cclk;
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for (i = 0; i < desc->num_clk_clks; i++) {
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cclk = desc->clk_clks[i];
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if (!cclk)
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continue;
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cclk->regmap = regmap;
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}
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}
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int sprd_clk_regmap_init(struct platform_device *pdev,
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const struct sprd_clk_desc *desc)
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{
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void __iomem *base;
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struct device_node *node = pdev->dev.of_node;
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struct regmap *regmap;
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if (of_find_property(node, "sprd,syscon", NULL)) {
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regmap = syscon_regmap_lookup_by_phandle(node, "sprd,syscon");
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if (IS_ERR(regmap)) {
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pr_err("%s: failed to get syscon regmap\n", __func__);
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return PTR_ERR(regmap);
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}
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} else {
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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regmap = devm_regmap_init_mmio(&pdev->dev, base,
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&sprdclk_regmap_config);
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if (IS_ERR(regmap)) {
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pr_err("failed to init regmap\n");
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return PTR_ERR(regmap);
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}
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}
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sprd_clk_set_regmap(desc, regmap);
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return 0;
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}
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EXPORT_SYMBOL_GPL(sprd_clk_regmap_init);
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int sprd_clk_probe(struct device *dev, struct clk_hw_onecell_data *clkhw)
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{
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int i, ret;
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struct clk_hw *hw;
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for (i = 0; i < clkhw->num; i++) {
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const char *name;
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hw = clkhw->hws[i];
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if (!hw)
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continue;
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name = hw->init->name;
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ret = devm_clk_hw_register(dev, hw);
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if (ret) {
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dev_err(dev, "Couldn't register clock %d - %s\n",
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i, name);
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return ret;
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}
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}
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ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clkhw);
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if (ret)
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dev_err(dev, "Failed to add clock provider\n");
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return ret;
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}
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EXPORT_SYMBOL_GPL(sprd_clk_probe);
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MODULE_LICENSE("GPL v2");
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