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7255f87a71
CTS signal can not be used for the port and tied to any logic state. In this case we have an infinite loop waiting for the signal. For fix this problem, checking CTS removed, waiting for the signal "busy" was postponed after the byte write to the port. Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
39 lines
849 B
ArmAsm
39 lines
849 B
ArmAsm
/* arch/arm/mach-clps711x/include/mach/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <mach/hardware.h>
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.macro addruart, rp, rv, tmp
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#ifndef CONFIG_DEBUG_CLPS711X_UART2
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mov \rp, #0x0000 @ UART1
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#else
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mov \rp, #0x1000 @ UART2
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#endif
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orr \rv, \rp, #CLPS711X_VIRT_BASE
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orr \rp, \rp, #CLPS711X_PHYS_BASE
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.endm
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.macro senduart,rd,rx
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str \rd, [\rx, #0x0480] @ UARTDR
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.endm
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.macro waituart,rd,rx
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.endm
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.macro busyuart,rd,rx
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1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx
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tst \rd, #1 << 11 @ UBUSYx
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bne 1001b
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.endm
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