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![Timur Tabi](/assets/img/avatar_default.png)
On Freescale parts with multiple MSI controllers, the controllers are combined into one "pool" of interrupts. Whenever a device requests an MSI interrupt, the next available interrupt from the pool is selected, regardless of which MSI controller the interrupt is from. This works because each PCI bus has an ATMU to all of CCSR, so any PCI device can access any MSI interrupt register. The fsl,msi property is used to specify that a given PCI bus should only use a specific MSI device. This is necessary, for example, with the Freescale hypervisor, because the MSI devices are assigned to specific partitions. Ideally, we'd like to be able to assign MSI devices to PCI busses within the MSI or PCI layers. However, there does not appear to be a mechanism to do that. Whenever the MSI layer wants to allocate an MSI interrupt to a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we could register an MSI device with a specific PCI bus. So instead we remember the phandles of each MSI device, and we use that to limit our search for an available interrupt. Whenever we are asked to allocate a new interrupt for a PCI device, we check the fsl,msi property of the PCI bus for that device. If it exists, then as we are looping over all MSI devices, we skip the ones that don't have a matching phandle. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
507 lines
12 KiB
C
507 lines
12 KiB
C
/*
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* Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
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*
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* Author: Tony Li <tony.li@freescale.com>
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* Jason Jin <Jason.jin@freescale.com>
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*
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* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#include <linux/irq.h>
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#include <linux/bootmem.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <linux/of_platform.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/prom.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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#include <asm/mpic.h>
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#include "fsl_msi.h"
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#include "fsl_pci.h"
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LIST_HEAD(msi_head);
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struct fsl_msi_feature {
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u32 fsl_pic_ip;
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u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
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};
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struct fsl_msi_cascade_data {
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struct fsl_msi *msi_data;
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int index;
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};
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static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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}
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/*
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* We do not need this actually. The MSIR register has been read once
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* in the cascade interrupt. So, this MSI interrupt has been acked
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*/
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static void fsl_msi_end_irq(struct irq_data *d)
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{
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}
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static struct irq_chip fsl_msi_chip = {
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.irq_mask = mask_msi_irq,
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.irq_unmask = unmask_msi_irq,
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.irq_ack = fsl_msi_end_irq,
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.name = "FSL-MSI",
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};
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static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct fsl_msi *msi_data = h->host_data;
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struct irq_chip *chip = &fsl_msi_chip;
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irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
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irq_set_chip_data(virq, msi_data);
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irq_set_chip_and_handler(virq, chip, handle_edge_irq);
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return 0;
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}
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static struct irq_host_ops fsl_msi_host_ops = {
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.map = fsl_msi_host_map,
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};
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static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
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{
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int rc;
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rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
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msi_data->irqhost->of_node);
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if (rc)
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return rc;
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rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
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if (rc < 0) {
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msi_bitmap_free(&msi_data->bitmap);
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return rc;
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}
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return 0;
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}
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static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
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{
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if (type == PCI_CAP_ID_MSIX)
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pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
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return 0;
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}
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static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct msi_desc *entry;
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struct fsl_msi *msi_data;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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msi_data = irq_get_chip_data(entry->irq);
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irq_set_msi_desc(entry->irq, NULL);
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msi_bitmap_free_hwirqs(&msi_data->bitmap,
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virq_to_hw(entry->irq), 1);
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irq_dispose_mapping(entry->irq);
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}
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return;
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}
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static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
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struct msi_msg *msg,
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struct fsl_msi *fsl_msi_data)
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{
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struct fsl_msi *msi_data = fsl_msi_data;
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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u64 address; /* Physical address of the MSIIR */
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int len;
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const u64 *reg;
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/* If the msi-address-64 property exists, then use it */
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reg = of_get_property(hose->dn, "msi-address-64", &len);
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if (reg && (len == sizeof(u64)))
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address = be64_to_cpup(reg);
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else
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address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
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msg->address_lo = lower_32_bits(address);
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msg->address_hi = upper_32_bits(address);
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msg->data = hwirq;
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pr_debug("%s: allocated srs: %d, ibs: %d\n",
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__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
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}
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static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct device_node *np;
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phandle phandle = 0;
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int rc, hwirq = -ENOMEM;
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unsigned int virq;
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struct msi_desc *entry;
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struct msi_msg msg;
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struct fsl_msi *msi_data;
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/*
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* If the PCI node has an fsl,msi property, then we need to use it
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* to find the specific MSI.
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*/
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np = of_parse_phandle(hose->dn, "fsl,msi", 0);
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if (np) {
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if (of_device_is_compatible(np, "fsl,mpic-msi"))
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phandle = np->phandle;
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else {
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dev_err(&pdev->dev, "node %s has an invalid fsl,msi"
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" phandle\n", hose->dn->full_name);
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return -EINVAL;
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}
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}
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list_for_each_entry(entry, &pdev->msi_list, list) {
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/*
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* Loop over all the MSI devices until we find one that has an
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* available interrupt.
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*/
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list_for_each_entry(msi_data, &msi_head, list) {
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/*
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* If the PCI node has an fsl,msi property, then we
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* restrict our search to the corresponding MSI node.
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* The simplest way is to skip over MSI nodes with the
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* wrong phandle. Under the Freescale hypervisor, this
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* has the additional benefit of skipping over MSI
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* nodes that are not mapped in the PAMU.
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*/
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if (phandle && (phandle != msi_data->phandle))
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continue;
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hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
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if (hwirq >= 0)
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break;
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}
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if (hwirq < 0) {
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rc = hwirq;
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pr_debug("%s: fail allocating msi interrupt\n",
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__func__);
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goto out_free;
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}
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virq = irq_create_mapping(msi_data->irqhost, hwirq);
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if (virq == NO_IRQ) {
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pr_debug("%s: fail mapping hwirq 0x%x\n",
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__func__, hwirq);
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msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
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rc = -ENOSPC;
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goto out_free;
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}
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/* chip_data is msi_data via host->hostdata in host->map() */
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irq_set_msi_desc(virq, entry);
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fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
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write_msi_msg(virq, &msg);
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}
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return 0;
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out_free:
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/* free by the caller of this function */
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return rc;
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}
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static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_chip *chip = irq_desc_get_chip(desc);
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struct irq_data *idata = irq_desc_get_irq_data(desc);
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unsigned int cascade_irq;
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struct fsl_msi *msi_data;
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int msir_index = -1;
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u32 msir_value = 0;
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u32 intr_index;
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u32 have_shift = 0;
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struct fsl_msi_cascade_data *cascade_data;
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cascade_data = irq_get_handler_data(irq);
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msi_data = cascade_data->msi_data;
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raw_spin_lock(&desc->lock);
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if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
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if (chip->irq_mask_ack)
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chip->irq_mask_ack(idata);
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else {
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chip->irq_mask(idata);
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chip->irq_ack(idata);
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}
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}
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if (unlikely(irqd_irq_inprogress(idata)))
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goto unlock;
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msir_index = cascade_data->index;
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if (msir_index >= NR_MSI_REG)
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cascade_irq = NO_IRQ;
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irqd_set_chained_irq_inprogress(idata);
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switch (msi_data->feature & FSL_PIC_IP_MASK) {
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case FSL_PIC_IP_MPIC:
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msir_value = fsl_msi_read(msi_data->msi_regs,
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msir_index * 0x10);
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break;
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case FSL_PIC_IP_IPIC:
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msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
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break;
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}
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while (msir_value) {
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intr_index = ffs(msir_value) - 1;
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cascade_irq = irq_linear_revmap(msi_data->irqhost,
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msir_index * IRQS_PER_MSI_REG +
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intr_index + have_shift);
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if (cascade_irq != NO_IRQ)
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generic_handle_irq(cascade_irq);
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have_shift += intr_index + 1;
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msir_value = msir_value >> (intr_index + 1);
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}
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irqd_clr_chained_irq_inprogress(idata);
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switch (msi_data->feature & FSL_PIC_IP_MASK) {
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case FSL_PIC_IP_MPIC:
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chip->irq_eoi(idata);
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break;
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case FSL_PIC_IP_IPIC:
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if (!irqd_irq_disabled(idata) && chip->irq_unmask)
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chip->irq_unmask(idata);
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break;
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}
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unlock:
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raw_spin_unlock(&desc->lock);
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}
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static int fsl_of_msi_remove(struct platform_device *ofdev)
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{
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struct fsl_msi *msi = platform_get_drvdata(ofdev);
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int virq, i;
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struct fsl_msi_cascade_data *cascade_data;
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if (msi->list.prev != NULL)
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list_del(&msi->list);
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for (i = 0; i < NR_MSI_REG; i++) {
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virq = msi->msi_virqs[i];
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if (virq != NO_IRQ) {
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cascade_data = irq_get_handler_data(virq);
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kfree(cascade_data);
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irq_dispose_mapping(virq);
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}
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}
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if (msi->bitmap.bitmap)
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msi_bitmap_free(&msi->bitmap);
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iounmap(msi->msi_regs);
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kfree(msi);
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return 0;
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}
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static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
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struct platform_device *dev,
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int offset, int irq_index)
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{
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struct fsl_msi_cascade_data *cascade_data = NULL;
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int virt_msir;
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virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
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if (virt_msir == NO_IRQ) {
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dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
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__func__, irq_index);
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return 0;
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}
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cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
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if (!cascade_data) {
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dev_err(&dev->dev, "No memory for MSI cascade data\n");
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return -ENOMEM;
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}
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msi->msi_virqs[irq_index] = virt_msir;
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cascade_data->index = offset;
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cascade_data->msi_data = msi;
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irq_set_handler_data(virt_msir, cascade_data);
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irq_set_chained_handler(virt_msir, fsl_msi_cascade);
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return 0;
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}
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static const struct of_device_id fsl_of_msi_ids[];
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static int __devinit fsl_of_msi_probe(struct platform_device *dev)
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{
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const struct of_device_id *match;
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struct fsl_msi *msi;
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struct resource res;
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int err, i, j, irq_index, count;
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int rc;
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const u32 *p;
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struct fsl_msi_feature *features;
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int len;
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u32 offset;
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static const u32 all_avail[] = { 0, NR_MSI_IRQS };
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match = of_match_device(fsl_of_msi_ids, &dev->dev);
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if (!match)
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return -EINVAL;
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features = match->data;
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printk(KERN_DEBUG "Setting up Freescale MSI support\n");
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msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
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if (!msi) {
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dev_err(&dev->dev, "No memory for MSI structure\n");
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return -ENOMEM;
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}
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platform_set_drvdata(dev, msi);
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msi->irqhost = irq_alloc_host(dev->dev.of_node, IRQ_HOST_MAP_LINEAR,
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NR_MSI_IRQS, &fsl_msi_host_ops, 0);
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if (msi->irqhost == NULL) {
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dev_err(&dev->dev, "No memory for MSI irqhost\n");
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err = -ENOMEM;
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goto error_out;
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}
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/* Get the MSI reg base */
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err = of_address_to_resource(dev->dev.of_node, 0, &res);
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if (err) {
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dev_err(&dev->dev, "%s resource error!\n",
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dev->dev.of_node->full_name);
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goto error_out;
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}
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msi->msi_regs = ioremap(res.start, resource_size(&res));
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if (!msi->msi_regs) {
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dev_err(&dev->dev, "ioremap problem failed\n");
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goto error_out;
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}
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msi->feature = features->fsl_pic_ip;
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msi->irqhost->host_data = msi;
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msi->msiir_offset = features->msiir_offset + (res.start & 0xfffff);
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/*
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* Remember the phandle, so that we can match with any PCI nodes
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* that have an "fsl,msi" property.
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*/
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msi->phandle = dev->dev.of_node->phandle;
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rc = fsl_msi_init_allocator(msi);
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if (rc) {
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dev_err(&dev->dev, "Error allocating MSI bitmap\n");
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goto error_out;
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}
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p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
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if (p && len % (2 * sizeof(u32)) != 0) {
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dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
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__func__);
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err = -EINVAL;
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goto error_out;
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}
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if (!p) {
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p = all_avail;
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len = sizeof(all_avail);
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}
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for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
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if (p[i * 2] % IRQS_PER_MSI_REG ||
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p[i * 2 + 1] % IRQS_PER_MSI_REG) {
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printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
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__func__, dev->dev.of_node->full_name,
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p[i * 2 + 1], p[i * 2]);
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err = -EINVAL;
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goto error_out;
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}
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offset = p[i * 2] / IRQS_PER_MSI_REG;
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count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
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for (j = 0; j < count; j++, irq_index++) {
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err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index);
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if (err)
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goto error_out;
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}
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}
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list_add_tail(&msi->list, &msi_head);
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/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
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if (!ppc_md.setup_msi_irqs) {
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ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
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ppc_md.msi_check_device = fsl_msi_check_device;
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} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
|
|
dev_err(&dev->dev, "Different MSI driver already installed!\n");
|
|
err = -ENODEV;
|
|
goto error_out;
|
|
}
|
|
return 0;
|
|
error_out:
|
|
fsl_of_msi_remove(dev);
|
|
return err;
|
|
}
|
|
|
|
static const struct fsl_msi_feature mpic_msi_feature = {
|
|
.fsl_pic_ip = FSL_PIC_IP_MPIC,
|
|
.msiir_offset = 0x140,
|
|
};
|
|
|
|
static const struct fsl_msi_feature ipic_msi_feature = {
|
|
.fsl_pic_ip = FSL_PIC_IP_IPIC,
|
|
.msiir_offset = 0x38,
|
|
};
|
|
|
|
static const struct of_device_id fsl_of_msi_ids[] = {
|
|
{
|
|
.compatible = "fsl,mpic-msi",
|
|
.data = (void *)&mpic_msi_feature,
|
|
},
|
|
{
|
|
.compatible = "fsl,ipic-msi",
|
|
.data = (void *)&ipic_msi_feature,
|
|
},
|
|
{}
|
|
};
|
|
|
|
static struct platform_driver fsl_of_msi_driver = {
|
|
.driver = {
|
|
.name = "fsl-msi",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = fsl_of_msi_ids,
|
|
},
|
|
.probe = fsl_of_msi_probe,
|
|
.remove = fsl_of_msi_remove,
|
|
};
|
|
|
|
static __init int fsl_of_msi_init(void)
|
|
{
|
|
return platform_driver_register(&fsl_of_msi_driver);
|
|
}
|
|
|
|
subsys_initcall(fsl_of_msi_init);
|