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885014bcf2
Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by: Felix Fietkau <nbd@openwrt.org> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5912/
25 lines
546 B
C
25 lines
546 B
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
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*
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*/
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#ifndef __ASM_DMA_COHERENCE_H
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#define __ASM_DMA_COHERENCE_H
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#ifdef CONFIG_DMA_MAYBE_COHERENT
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extern int coherentio;
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extern int hw_coherentio;
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#else
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#ifdef CONFIG_DMA_COHERENT
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#define coherentio 1
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#else
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#define coherentio 0
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#endif
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#define hw_coherentio 0
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#endif /* CONFIG_DMA_MAYBE_COHERENT */
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#endif
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