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Based on 1 normalized pattern(s): the code contained herein is licensed under the gnu general public license you may obtain a copy of the gnu general public license version 2 or later at the following locations http www opensource org licenses gpl license html http www gnu org copyleft gpl html extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.383790741@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
124 lines
2.9 KiB
C
124 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*/
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#include <linux/init.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/page.h>
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#include <asm/smp_scu.h>
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#include <asm/mach/map.h>
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#include "common.h"
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#include "hardware.h"
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u32 g_diag_reg;
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static void __iomem *scu_base;
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static struct map_desc scu_io_desc __initdata = {
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/* .virtual and .pfn are run-time assigned */
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.length = SZ_4K,
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.type = MT_DEVICE,
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};
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void __init imx_scu_map_io(void)
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{
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unsigned long base;
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/* Get SCU base */
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asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
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scu_io_desc.virtual = IMX_IO_P2V(base);
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scu_io_desc.pfn = __phys_to_pfn(base);
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iotable_init(&scu_io_desc, 1);
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scu_base = IMX_IO_ADDRESS(base);
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}
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static int imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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imx_set_cpu_jump(cpu, v7_secondary_startup);
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imx_enable_cpu(cpu, true);
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return 0;
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}
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/*
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* Initialise the CPU possible map early - this describes the CPUs
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* which may be present or become present in the system.
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*/
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static void __init imx_smp_init_cpus(void)
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{
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int i, ncores;
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ncores = scu_get_core_count(scu_base);
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for (i = ncores; i < NR_CPUS; i++)
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set_cpu_possible(i, false);
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}
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void imx_smp_prepare(void)
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{
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scu_enable(scu_base);
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}
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static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
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{
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imx_smp_prepare();
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/*
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* The diagnostic register holds the errata bits. Mostly bootloader
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* does not bring up secondary cores, so that when errata bits are set
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* in bootloader, they are set only for boot cpu. But on a SMP
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* configuration, it should be equally done on every single core.
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* Read the register from boot cpu here, and will replicate it into
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* secondary cores when booting them.
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*/
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asm("mrc p15, 0, %0, c15, c0, 1" : "=r" (g_diag_reg) : : "cc");
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sync_cache_w(&g_diag_reg);
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}
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const struct smp_operations imx_smp_ops __initconst = {
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.smp_init_cpus = imx_smp_init_cpus,
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.smp_prepare_cpus = imx_smp_prepare_cpus,
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.smp_boot_secondary = imx_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = imx_cpu_die,
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.cpu_kill = imx_cpu_kill,
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#endif
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};
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#define DCFG_CCSR_SCRATCHRW1 0x200
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static int ls1021a_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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arch_send_wakeup_ipi_mask(cpumask_of(cpu));
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return 0;
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}
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static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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void __iomem *dcfg_base;
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unsigned long paddr;
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np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
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dcfg_base = of_iomap(np, 0);
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BUG_ON(!dcfg_base);
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paddr = __pa_symbol(secondary_startup);
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writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
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iounmap(dcfg_base);
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}
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const struct smp_operations ls1021a_smp_ops __initconst = {
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.smp_prepare_cpus = ls1021a_smp_prepare_cpus,
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.smp_boot_secondary = ls1021a_boot_secondary,
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};
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