Adrian Hunter 690ca3a306 x86/insn: Add support for APX EVEX instructions to the opcode map ... To support APX functionality, the EVEX prefix is used to: - promote legacy instructions - promote VEX instructions - add new instructions Promoted VEX instructions require no extra annotation because the opcodes do not change and the permissive nature of the instruction decoder already allows them to have an EVEX prefix. Promoted legacy instructions and new instructions are placed in map 4 which has not been used before. Create a new table for map 4 and add APX instructions. Annotate SCALABLE instructions with "(es)" - refer to patch "x86/insn: Add support for APX EVEX to the instruction decoder logic". SCALABLE instructions must be represented in both no-prefix (NP) and 66 prefix forms. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ingo Molnar <mingo@kernel.org> Link: https://lore.kernel.org/r/20240502105853.5338-9-adrian.hunter@intel.com		2024-05-02 13:13:46 +02:00
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inat.c	x86/insn: Add a __ignore_sync_check__ marker	2021-03-15 11:00:57 +01:00
insn.c	x86/insn: Add support for APX EVEX to the instruction decoder logic	2024-05-02 13:13:45 +02:00
memcpy_64.S	tools headers: Update the copy of x86's mem{cpy,set}_64.S used in 'perf bench'	2024-01-30 11:31:15 -03:00
memset_64.S	tools headers: Update the copy of x86's mem{cpy,set}_64.S used in 'perf bench'	2024-01-30 11:31:15 -03:00
x86-opcode-map.txt	x86/insn: Add support for APX EVEX instructions to the opcode map	2024-05-02 13:13:46 +02:00