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a4de58a909
Some SoCs like gs101 don't fit in well with the existing pll lock and clock data recovery (CDR) callback used by existing exynos platforms. Allow SoCs to specifify and implement their own calibration and CDR functions that can be called by the generic samsung phy code. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240404122559.898930-11-peter.griffin@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
65 lines
2 KiB
C
65 lines
2 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* UFS PHY driver data for FSD SoC
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*
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* Copyright (C) 2022 Samsung Electronics Co., Ltd.
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*
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*/
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#include "phy-samsung-ufs.h"
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#define FSD_EMBEDDED_COMBO_PHY_CTRL 0x724
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#define FSD_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1
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#define FSD_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0)
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#define FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS 0x6e
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static const struct samsung_ufs_phy_cfg fsd_pre_init_cfg[] = {
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PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY),
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PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY),
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PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY),
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END_UFS_PHY_CFG
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};
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/* Calibration for HS mode series A/B */
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static const struct samsung_ufs_phy_cfg fsd_pre_pwr_hs_cfg[] = {
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END_UFS_PHY_CFG
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};
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/* Calibration for HS mode series A/B atfer PMC */
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static const struct samsung_ufs_phy_cfg fsd_post_pwr_hs_cfg[] = {
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END_UFS_PHY_CFG
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};
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static const struct samsung_ufs_phy_cfg *fsd_ufs_phy_cfgs[CFG_TAG_MAX] = {
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[CFG_PRE_INIT] = fsd_pre_init_cfg,
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[CFG_PRE_PWR_HS] = fsd_pre_pwr_hs_cfg,
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[CFG_POST_PWR_HS] = fsd_post_pwr_hs_cfg,
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};
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static const char * const fsd_ufs_phy_clks[] = {
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"ref_clk",
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};
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const struct samsung_ufs_phy_drvdata fsd_ufs_phy = {
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.cfgs = fsd_ufs_phy_cfgs,
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.isol = {
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.offset = FSD_EMBEDDED_COMBO_PHY_CTRL,
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.mask = FSD_EMBEDDED_COMBO_PHY_CTRL_MASK,
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.en = FSD_EMBEDDED_COMBO_PHY_CTRL_EN,
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},
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.clk_list = fsd_ufs_phy_clks,
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.num_clks = ARRAY_SIZE(fsd_ufs_phy_clks),
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.cdr_lock_status_offset = FSD_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
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.wait_for_cdr = samsung_ufs_phy_wait_for_lock_acq,
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};
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