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163c1a356a
Currently, none of the X1E80100 supported boards upstream have enabled
DP. As for USB, the reason it is not broken when it's obvious that the
offsets are wrong is because the only difference with respect to USB is
the difference in register name. The V6 uses QPHY_V6_PCS_CDR_RESET_TIME
while V6 N4 uses QPHY_V6_N4_PCS_RX_CONFIG. Now, in order for the DP to
work, the DP serdes tables need to be added as they have different
values for V6 N4 when compared to V6 ones, even though they use the same
V6 offsets. While at it, switch swing and pre-emphasis tables to V6 as
well.
Fixes: d7b3579f84 ("phy: qcom-qmp-combo: Add x1e80100 USB/DP combo phys")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-3-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
81 lines
1.9 KiB
C
81 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_H_
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#define QCOM_PHY_QMP_H_
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#include "phy-qcom-qmp-qserdes-com.h"
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#include "phy-qcom-qmp-qserdes-txrx.h"
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#include "phy-qcom-qmp-qserdes-com-v3.h"
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#include "phy-qcom-qmp-qserdes-txrx-v3.h"
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#include "phy-qcom-qmp-qserdes-com-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4.h"
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#include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
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#include "phy-qcom-qmp-qserdes-com-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
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#include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
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#include "phy-qcom-qmp-qserdes-com-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
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#include "phy-qcom-qmp-qserdes-txrx-v6_n4.h"
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#include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
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#include "phy-qcom-qmp-qserdes-com-v7.h"
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#include "phy-qcom-qmp-qserdes-txrx-v7.h"
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#include "phy-qcom-qmp-qserdes-pll.h"
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#include "phy-qcom-qmp-pcs-v2.h"
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#include "phy-qcom-qmp-pcs-v3.h"
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#include "phy-qcom-qmp-pcs-v4.h"
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#include "phy-qcom-qmp-pcs-v4_20.h"
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#include "phy-qcom-qmp-pcs-v5.h"
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#include "phy-qcom-qmp-pcs-v5_20.h"
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#include "phy-qcom-qmp-pcs-v6.h"
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#include "phy-qcom-qmp-pcs-v6-n4.h"
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#include "phy-qcom-qmp-pcs-v6_20.h"
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#include "phy-qcom-qmp-pcs-v7.h"
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/* QPHY_SW_RESET bit */
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#define SW_RESET BIT(0)
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/* QPHY_POWER_DOWN_CONTROL */
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#define SW_PWRDN BIT(0)
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#define REFCLK_DRV_DSBL BIT(1) /* PCIe */
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/* QPHY_START_CONTROL bits */
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#define SERDES_START BIT(0)
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#define PCS_START BIT(1)
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/* QPHY_PCS_STATUS bit */
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#define PHYSTATUS BIT(6)
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#define PHYSTATUS_4_20 BIT(7)
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/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
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#define ARCVR_DTCT_EN BIT(0)
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#define ALFPS_DTCT_EN BIT(1)
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#define ARCVR_DTCT_EVENT_SEL BIT(4)
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/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
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#define IRQ_CLEAR BIT(0)
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/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
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#define CLAMP_EN BIT(0) /* enables i/o clamp_n */
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#endif
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