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5314e84c33
Currently, the x1e80100 uses pure V6 register offsets for DP part of the
combo PHY. This hasn't been an issue because external DP is not yet
enabled on any of the boards yet. But in order to enabled it, all these
new V6 N4 register offsets are needed. So add them.
Fixes: 762c3565f3 ("phy: qcom-qmp: qserdes-txrx: Add V6 N4 register offsets")
Co-developed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240527-x1e80100-phy-qualcomm-combo-fix-dp-v1-1-be8a0b882117@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
65 lines
2.7 KiB
C
65 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
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#define QSERDES_V6_N4_TX_CLKBUF_ENABLE 0x08
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#define QSERDES_V6_N4_TX_TX_EMP_POST1_LVL 0x0c
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#define QSERDES_V6_N4_TX_TX_DRV_LVL 0x14
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#define QSERDES_V6_N4_TX_RESET_TSYNC_EN 0x1c
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#define QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN 0x20
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#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX 0x30
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#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX 0x34
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#define QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN 0x48
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#define QSERDES_V6_N4_TX_HIGHZ_DRVR_EN 0x4c
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#define QSERDES_V6_N4_TX_TX_POL_INV 0x50
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#define QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN 0x54
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#define QSERDES_V6_N4_TX_LANE_MODE_1 0x78
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#define QSERDES_V6_N4_TX_LANE_MODE_2 0x7c
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#define QSERDES_V6_N4_TX_LANE_MODE_3 0x80
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#define QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN 0xac
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#define QSERDES_V6_N4_TX_TX_BAND 0xd8
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#define QSERDES_V6_N4_TX_INTERFACE_SELECT 0xe4
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#define QSERDES_V6_N4_TX_VMODE_CTRL1 0xb0
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#define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2 0x8
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#define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2 0x18
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#define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS 0x20
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#define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE 0x94
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#define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2 0x9c
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#define QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET 0xa0
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#define QSERDES_V6_N4_RX_DFE_3 0xb4
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#define QSERDES_V6_N4_RX_VGA_CAL_CNTRL1 0xe0
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#define QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL 0xe8
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#define QSERDES_V6_N4_RX_GM_CAL 0x10c
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#define QSERDES_V6_N4_RX_SIGDET_ENABLES 0x148
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#define QSERDES_V6_N4_RX_SIGDET_CNTRL 0x14c
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#define QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL 0x154
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#define QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET 0x194
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#define QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32 0x1dc
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#define QSERDES_V6_N4_RX_UCDR_PI_CTRL1 0x23c
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#define QSERDES_V6_N4_RX_UCDR_PI_CTRL2 0x240
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#define QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2 0x27c
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#define QSERDES_V6_N4_RX_DFE_DAC_ENABLE1 0x298
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#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B0 0x2b8
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#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B1 0x2bc
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#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B2 0x2c0
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#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B3 0x2c4
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#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B4 0x2c8
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#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B5 0x2cc
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#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B6 0x2d0
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#define QSERDES_V6_N4_RX_MODE_RATE2_B0 0x2d4
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#define QSERDES_V6_N4_RX_MODE_RATE2_B1 0x2d8
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#define QSERDES_V6_N4_RX_MODE_RATE2_B2 0x2dc
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#define QSERDES_V6_N4_RX_MODE_RATE2_B3 0x2e0
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#define QSERDES_V6_N4_RX_MODE_RATE2_B4 0x2e4
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#define QSERDES_V6_N4_RX_MODE_RATE2_B5 0x2e8
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#define QSERDES_V6_N4_RX_MODE_RATE2_B6 0x2ec
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#define QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE 0x30c
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#define QSERDES_V6_N4_RX_RX_BKUP_CTRL1 0x310
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#endif
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