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b9251e64a9
Update the SM8650 UFS PHY init tables to support Gear 4 and Gear 5 using the overlays setup (only supported Gear 5 before), and sync back with the latest Qualcomm recommended values. The new recommended values allow a solid 50% bump in sequential read/write benchmarks on the SM8650 QRD & HDK reference boards. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240410-topic-sm8650-upstream-ufs-g5-v1-1-5527c44b37e6@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
53 lines
2.2 KiB
C
53 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
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#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX 0x28
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30
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#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34
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#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c
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#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4 0x24
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#define QSERDES_UFS_V6_RX_UCDR_SO_SATURATION 0x28
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#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4 0x54
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#define QSERDES_UFS_V6_RX_UCDR_PI_CTRL1 0x58
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#define QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0 0xc4
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#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4
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#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4 0xdc
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#define QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4 0xf0
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#define QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS 0xf4
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#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178
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#define QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4 0x1ac
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#define QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x1bc
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#define QSERDES_UFS_V6_RX_INTERFACE_MODE 0x1e0
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#define QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3 0x1c4
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2 0x210
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3 0x214
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4 0x218
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#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6 0x220
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#define QSERDES_UFS_V6_RX_MODE_RATE2_B3 0x238
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#define QSERDES_UFS_V6_RX_MODE_RATE2_B6 0x244
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B3 0x25c
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B4 0x260
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B5 0x264
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#define QSERDES_UFS_V6_RX_MODE_RATE3_B8 0x270
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B0 0x274
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B1 0x278
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B2 0x27c
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B3 0x280
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B4 0x284
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#define QSERDES_UFS_V6_RX_MODE_RATE4_B6 0x28c
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#define QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL 0x2f8
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#endif
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