linux/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
Abel Vesa d38360e12f phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
The new SM8550 SoC bumps up the HW version of QMP phy to v6.20 for
PCIE g4x2. Add the new lane shared PCIE specific offsets in a dedicated
header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230208180020.2761766-8-abel.vesa@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2023-02-10 22:28:00 +05:30

33 lines
1.4 KiB
C

/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
#define QCOM_PHY_QMP_QSERDES_LN_SHRD_V6_H_
#define QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL 0xa0
#define QSERDES_V6_LN_SHRD_RX_Q_EN_RATES 0xb0
#define QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1 0xb4
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1 0xc4
#define QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2 0xc8
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0 0xd4
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1 0xd8
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2 0xdc
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3 0xe0
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4 0xe4
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5 0xe8
#define QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6 0xec
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210 0xf0
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3 0xf4
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210 0xf8
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3 0xfc
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210 0x100
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3 0x104
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3 0x10c
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3 0x114
#define QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3 0x11c
#define QSERDES_V6_LN_SHRD_RX_SUMMER_CAL_SPD_MODE 0x128
#endif