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bc546cc85c
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB and PCIE g3x2. Add the new qserdes com offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-5-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
88 lines
3.7 KiB
C
88 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_QSERDES_COM_V7_H_
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#define QCOM_PHY_QMP_QSERDES_COM_V7_H_
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/* Only for QMP V7 PHY - QSERDES COM registers */
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#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1 0x00
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#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1 0x04
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#define QSERDES_V7_COM_CP_CTRL_MODE1 0x10
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#define QSERDES_V7_COM_PLL_RCTRL_MODE1 0x14
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#define QSERDES_V7_COM_PLL_CCTRL_MODE1 0x18
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#define QSERDES_V7_COM_CORECLK_DIV_MODE1 0x1c
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#define QSERDES_V7_COM_LOCK_CMP1_MODE1 0x20
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#define QSERDES_V7_COM_LOCK_CMP2_MODE1 0x24
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#define QSERDES_V7_COM_DEC_START_MODE1 0x28
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#define QSERDES_V7_COM_DEC_START_MSB_MODE1 0x2c
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#define QSERDES_V7_COM_DIV_FRAC_START1_MODE1 0x30
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#define QSERDES_V7_COM_DIV_FRAC_START2_MODE1 0x34
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#define QSERDES_V7_COM_DIV_FRAC_START3_MODE1 0x38
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#define QSERDES_V7_COM_HSCLK_SEL_1 0x3c
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#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE1 0x40
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#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE1 0x44
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#define QSERDES_V7_COM_VCO_TUNE1_MODE1 0x48
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#define QSERDES_V7_COM_VCO_TUNE2_MODE1 0x4c
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#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x50
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#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x54
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#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x58
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#define QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x5c
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#define QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0 0x60
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#define QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0 0x64
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#define QSERDES_V7_COM_CP_CTRL_MODE0 0x70
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#define QSERDES_V7_COM_PLL_RCTRL_MODE0 0x74
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#define QSERDES_V7_COM_PLL_CCTRL_MODE0 0x78
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#define QSERDES_V7_COM_PLL_CORE_CLK_DIV_MODE0 0x7c
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#define QSERDES_V7_COM_LOCK_CMP1_MODE0 0x80
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#define QSERDES_V7_COM_LOCK_CMP2_MODE0 0x84
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#define QSERDES_V7_COM_DEC_START_MODE0 0x88
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#define QSERDES_V7_COM_DEC_START_MSB_MODE0 0x8c
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#define QSERDES_V7_COM_DIV_FRAC_START1_MODE0 0x90
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#define QSERDES_V7_COM_DIV_FRAC_START2_MODE0 0x94
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#define QSERDES_V7_COM_DIV_FRAC_START3_MODE0 0x98
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#define QSERDES_V7_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
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#define QSERDES_V7_COM_INTEGLOOP_GAIN0_MODE0 0xa0
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#define QSERDES_V7_COM_INTEGLOOP_GAIN1_MODE0 0xa4
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#define QSERDES_V7_COM_VCO_TUNE1_MODE0 0xa8
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#define QSERDES_V7_COM_VCO_TUNE2_MODE0 0xac
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#define QSERDES_V7_COM_BG_TIMER 0xbc
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#define QSERDES_V7_COM_SSC_EN_CENTER 0xc0
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#define QSERDES_V7_COM_SSC_ADJ_PER1 0xc4
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#define QSERDES_V7_COM_SSC_PER1 0xcc
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#define QSERDES_V7_COM_SSC_PER2 0xd0
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#define QSERDES_V7_COM_PLL_POST_DIV_MUX 0xd8
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#define QSERDES_V7_COM_PLL_BIAS_EN_CLK_BUFLR_EN 0xdc
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#define QSERDES_V7_COM_CLK_ENABLE1 0xe0
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#define QSERDES_V7_COM_SYS_CLK_CTRL 0xe4
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#define QSERDES_V7_COM_SYSCLK_BUF_ENABLE 0xe8
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#define QSERDES_V7_COM_PLL_IVCO 0xf4
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#define QSERDES_V7_COM_PLL_IVCO_MODE1 0xf8
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#define QSERDES_V7_COM_SYSCLK_EN_SEL 0x110
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#define QSERDES_V7_COM_RESETSM_CNTRL 0x118
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#define QSERDES_V7_COM_LOCK_CMP_EN 0x120
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#define QSERDES_V7_COM_LOCK_CMP_CFG 0x124
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#define QSERDES_V7_COM_VCO_TUNE_CTRL 0x13c
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#define QSERDES_V7_COM_VCO_TUNE_MAP 0x140
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#define QSERDES_V7_COM_VCO_TUNE_INITVAL2 0x148
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#define QSERDES_V7_COM_VCO_TUNE_MAXVAL2 0x158
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#define QSERDES_V7_COM_CLK_SELECT 0x164
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#define QSERDES_V7_COM_CORE_CLK_EN 0x170
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#define QSERDES_V7_COM_CMN_CONFIG_1 0x174
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#define QSERDES_V7_COM_SVS_MODE_CLK_SEL 0x17c
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#define QSERDES_V7_COM_CMN_MISC_1 0x184
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#define QSERDES_V7_COM_CMN_MODE 0x188
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#define QSERDES_V7_COM_PLL_VCO_DC_LEVEL_CTRL 0x198
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#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4
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#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8
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#define QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac
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#define QSERDES_V7_COM_ADDITIONAL_MISC 0x1b4
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#define QSERDES_V7_COM_ADDITIONAL_MISC_2 0x1b8
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#define QSERDES_V7_COM_ADDITIONAL_MISC_3 0x1bc
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#define QSERDES_V7_COM_CMN_STATUS 0x1d0
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#define QSERDES_V7_COM_C_READY_STATUS 0x1f8
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#endif
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