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7b98cf0e9b
The X1E80100 platform bumps the HW version of QMP phy to v7 for USB, and PCIe. Add the new PCS offsets in a dedicated header file. Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-3-dfd1c375ef61@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_V7_H_
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#define QCOM_PHY_QMP_PCS_V7_H_
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/* Only for QMP V7 PHY - USB/PCIe PCS registers */
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#define QPHY_V7_PCS_SW_RESET 0x000
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#define QPHY_V7_PCS_PCS_STATUS1 0x014
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#define QPHY_V7_PCS_POWER_DOWN_CONTROL 0x040
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#define QPHY_V7_PCS_START_CONTROL 0x044
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#define QPHY_V7_PCS_POWER_STATE_CONFIG1 0x090
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#define QPHY_V7_PCS_LOCK_DETECT_CONFIG1 0x0c4
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#define QPHY_V7_PCS_LOCK_DETECT_CONFIG2 0x0c8
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#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3 0x0cc
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#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6 0x0d8
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#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1 0x0dc
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#define QPHY_V7_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L 0x190
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#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H 0x194
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#define QPHY_V7_PCS_RATE_SLEW_CNTRL1 0x198
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#define QPHY_V7_PCS_CDR_RESET_TIME 0x1b0
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#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG1 0x1c0
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#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG2 0x1c4
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#define QPHY_V7_PCS_PCS_TX_RX_CONFIG 0x1d0
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#define QPHY_V7_PCS_EQ_CONFIG1 0x1dc
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#define QPHY_V7_PCS_EQ_CONFIG2 0x1e0
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#define QPHY_V7_PCS_EQ_CONFIG5 0x1ec
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#endif
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