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06e3472882
Align PCIe1 PHY settings with SM8550 latest PCIe PHY Hardware Programming Guide. Signed-off-by: Can Guo <quic_cang@quicinc.com> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Link: https://lore.kernel.org/r/1703742157-69840-2-git-send-email-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
20 lines
581 B
C
20 lines
581 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_V6_20_H_
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#define QCOM_PHY_QMP_PCS_V6_20_H_
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/* Only for QMP V6_20 PHY - USB/PCIe PCS registers */
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#define QPHY_V6_20_PCS_G12S1_TXDEEMPH_M6DB 0x170
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#define QPHY_V6_20_PCS_G3S2_PRE_GAIN 0x178
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#define QPHY_V6_20_PCS_RX_SIGDET_LVL 0x190
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#define QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL 0x1b8
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#define QPHY_V6_20_PCS_TX_RX_CONFIG1 0x1dc
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#define QPHY_V6_20_PCS_TX_RX_CONFIG2 0x1e0
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#define QPHY_V6_20_PCS_EQ_CONFIG4 0x1f8
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#define QPHY_V6_20_PCS_EQ_CONFIG5 0x1fc
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#endif
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