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8e11a94e15
Add support for dual lane end point mode PHY found on sa8755p platform. Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/1697715430-30820-4-git-send-email-quic_msarkar@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
18 lines
467 B
C
18 lines
467 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022, Linaro Ltd.
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*/
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#ifndef QCOM_PHY_QMP_PCS_V5_20_H_
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#define QCOM_PHY_QMP_PCS_V5_20_H_
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#define QPHY_V5_20_PCS_INSIG_SW_CTRL7 0x060
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#define QPHY_V5_20_PCS_INSIG_MX_CTRL7 0x07c
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#define QPHY_V5_20_PCS_G3S2_PRE_GAIN 0x170
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#define QPHY_V5_20_PCS_RX_SIGDET_LVL 0x188
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#define QPHY_V5_20_PCS_EQ_CONFIG2 0x1d8
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#define QPHY_V5_20_PCS_EQ_CONFIG4 0x1e0
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#define QPHY_V5_20_PCS_EQ_CONFIG5 0x1e4
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#endif
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