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https://github.com/torvalds/linux
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b9251e64a9
Update the SM8650 UFS PHY init tables to support Gear 4 and Gear 5 using the overlays setup (only supported Gear 5 before), and sync back with the latest Qualcomm recommended values. The new recommended values allow a solid 50% bump in sequential read/write benchmarks on the SM8650 QRD & HDK reference boards. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240410-topic-sm8650-upstream-ufs-g5-v1-1-5527c44b37e6@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
39 lines
1.5 KiB
C
39 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_
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#define QCOM_PHY_QMP_PCS_UFS_V6_H_
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/* Only for QMP V6 PHY - UFS PCS registers */
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#define QPHY_V6_PCS_UFS_PHY_START 0x000
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#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V6_PCS_UFS_SW_RESET 0x008
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V6_PCS_UFS_PCS_CTRL1 0x020
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#define QPHY_V6_PCS_UFS_PLL_CNTL 0x02c
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#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
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#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0bc
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#define QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY 0x12c
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#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL 0x158
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#define QPHY_V6_PCS_UFS_LINECFG_DISABLE 0x17c
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#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME 0x184
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#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2 0x18c
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#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND 0x178
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#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND 0x174
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#define QPHY_V6_PCS_UFS_READY_STATUS 0x1a8
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#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1 0x1f4
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#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1 0x1fc
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#define QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME 0x220
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4 0x240
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5 0x244
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6 0x248
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#define QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7 0x24c
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#endif
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