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692b655160
UFS PHY in SM8250 SoC is capable of operating at HS G4 mode. Hence, add the required register settings using the tables_hs_g4 struct instance. This also requires a separate qmp_phy_cfg for SM8250 instead of reusing SM8150. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230114071009.88102-9-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
33 lines
1.2 KiB
C
33 lines
1.2 KiB
C
/* Only for QMP V5 PHY - UFS PCS registers */
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017, The Linux Foundation. All rights reserved.
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*/
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#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_
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#define QCOM_PHY_QMP_PCS_UFS_V5_H_
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/* Only for QMP V5 PHY - UFS PCS registers */
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#define QPHY_V5_PCS_UFS_PHY_START 0x000
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#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL 0x004
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#define QPHY_V5_PCS_UFS_SW_RESET 0x008
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c
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#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010
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#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c
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#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030
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#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038
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#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060
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#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074
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#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4
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#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124
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#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150
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#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154
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#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158
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#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160
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#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168
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#define QPHY_V5_PCS_UFS_READY_STATUS 0x180
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#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8
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#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0
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#endif
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