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80082fc89e
Align PCIe0 PHY settings with SM8550 latest PCIe PHY Hardware Programming Guide. Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK Link: https://lore.kernel.org/r/1703742157-69840-3-git-send-email-quic_qianyu@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
18 lines
547 B
C
18 lines
547 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Linaro Limited
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*/
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#ifndef QCOM_PHY_QMP_PCS_PCIE_V6_H_
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#define QCOM_PHY_QMP_PCS_PCIE_V6_H_
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/* Only for QMP V6 PHY - PCIE have different offsets than V5 */
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#define QPHY_PCIE_V6_PCS_PCIE_EQ_CONFIG1 0xa4
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#define QPHY_PCIE_V6_PCS_PCIE_RXEQEVAL_TIME 0xf4
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#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2 0x0c
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#define QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4 0x14
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#define QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20
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#define QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS 0x94
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#endif
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