mirror of
https://github.com/torvalds/linux
synced 2024-07-21 10:41:44 +00:00
364c748d5e
Add PCIe RC init sequence making use of the common init sequence. The RC mode additionally requires REFCLK_DRV_DSBL bit to set during powerup and powerdown. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Link: https://lore.kernel.org/r/20230308082424.140224-13-manivannan.sadhasivam@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
20 lines
659 B
C
20 lines
659 B
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2017, The Linux Foundation. All rights reserved.
|
|
*/
|
|
|
|
#ifndef QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
|
|
#define QCOM_PHY_QMP_PCS_PCIE_V4_20_H_
|
|
|
|
#define QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c
|
|
#define QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090
|
|
#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0
|
|
#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0
|
|
#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4
|
|
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc
|
|
#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108
|
|
#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824
|
|
#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828
|
|
|
|
#endif
|