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442f34ede7
This is a new driver that supports the MIPI CSI CD-PHY version 0.5 The number of PHYs depend on the SoC. Each PHY can support D-PHY only or CD-PHY configuration. The driver supports only D-PHY mode, so CD-PHY compatible PHY are configured in D-PHY mode. [Julien Stephan: simplify driver model: one instance per phy vs one instance for all phys] Signed-off-by: Louis Kuo <louis.kuo@mediatek.com> Signed-off-by: Phi-bang Nguyen <pnguyen@baylibre.com> [Julien Stephan: refactor code] Co-developed-by: Julien Stephan <jstephan@baylibre.com> Signed-off-by: Julien Stephan <jstephan@baylibre.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20240111101738.468916-1-jstephan@baylibre.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
63 lines
2 KiB
C
63 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, MediaTek Inc.
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* Copyright (c) 2023, BayLibre Inc.
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*/
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#ifndef __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__
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#define __PHY_MTK_MIPI_CSI_V_0_5_RX_REG_H__
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/*
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* CSI1 and CSI2 are identical, and similar to CSI0. All CSIX macros are
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* applicable to the three PHYs. Where differences exist, they are denoted by
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* macro names using CSI0 and CSI1, the latter being applicable to CSI1 and
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* CSI2 alike.
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*/
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#define MIPI_RX_ANA00_CSIXA 0x0000
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#define RG_CSI0A_CPHY_EN BIT(0)
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#define RG_CSIXA_EQ_PROTECT_EN BIT(1)
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#define RG_CSIXA_BG_LPF_EN BIT(2)
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#define RG_CSIXA_BG_CORE_EN BIT(3)
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#define RG_CSIXA_DPHY_L0_CKMODE_EN BIT(5)
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#define RG_CSIXA_DPHY_L0_CKSEL BIT(6)
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#define RG_CSIXA_DPHY_L1_CKMODE_EN BIT(8)
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#define RG_CSIXA_DPHY_L1_CKSEL BIT(9)
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#define RG_CSIXA_DPHY_L2_CKMODE_EN BIT(11)
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#define RG_CSIXA_DPHY_L2_CKSEL BIT(12)
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#define MIPI_RX_ANA18_CSIXA 0x0018
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#define RG_CSI0A_L0_T0AB_EQ_IS GENMASK(5, 4)
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#define RG_CSI0A_L0_T0AB_EQ_BW GENMASK(7, 6)
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#define RG_CSI0A_L1_T1AB_EQ_IS GENMASK(21, 20)
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#define RG_CSI0A_L1_T1AB_EQ_BW GENMASK(23, 22)
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#define RG_CSI0A_L2_T1BC_EQ_IS GENMASK(21, 20)
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#define RG_CSI0A_L2_T1BC_EQ_BW GENMASK(23, 22)
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#define RG_CSI1A_L0_EQ_IS GENMASK(5, 4)
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#define RG_CSI1A_L0_EQ_BW GENMASK(7, 6)
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#define RG_CSI1A_L1_EQ_IS GENMASK(21, 20)
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#define RG_CSI1A_L1_EQ_BW GENMASK(23, 22)
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#define RG_CSI1A_L2_EQ_IS GENMASK(5, 4)
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#define RG_CSI1A_L2_EQ_BW GENMASK(7, 6)
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#define MIPI_RX_ANA1C_CSIXA 0x001c
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#define MIPI_RX_ANA20_CSI0A 0x0020
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#define MIPI_RX_ANA24_CSIXA 0x0024
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#define RG_CSIXA_RESERVE GENMASK(31, 24)
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#define MIPI_RX_ANA40_CSIXA 0x0040
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#define RG_CSIXA_CPHY_FMCK_SEL GENMASK(1, 0)
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#define RG_CSIXA_ASYNC_OPTION GENMASK(7, 4)
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#define RG_CSIXA_CPHY_SPARE GENMASK(31, 16)
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#define MIPI_RX_WRAPPER80_CSIXA 0x0080
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#define CSR_CSI_RST_MODE GENMASK(17, 16)
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#define MIPI_RX_ANAA8_CSIXA 0x00a8
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#define RG_CSIXA_CDPHY_L0_T0_BYTECK_INVERT BIT(0)
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#define RG_CSIXA_DPHY_L1_BYTECK_INVERT BIT(1)
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#define RG_CSIXA_CDPHY_L2_T1_BYTECK_INVERT BIT(2)
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#endif
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