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For the individual CCU drivers to be built as modules, the ops structs, helper functions, and callback registration functions must be exported. These symbols are intended for use only by the adjacent CCU drivers, so export them into the SUNXI_CCU namespace. of_sunxi_ccu_probe is not exported because it is only used by built-in OF clock providers. Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Link: https://lore.kernel.org/r/20211119033338.25486-2-samuel@sholland.org
125 lines
3.1 KiB
C
125 lines
3.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/spinlock.h>
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#include "ccu_phase.h"
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static int ccu_phase_get_phase(struct clk_hw *hw)
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{
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struct ccu_phase *phase = hw_to_ccu_phase(hw);
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struct clk_hw *parent, *grandparent;
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unsigned int parent_rate, grandparent_rate;
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u16 step, parent_div;
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u32 reg;
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u8 delay;
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reg = readl(phase->common.base + phase->common.reg);
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delay = (reg >> phase->shift);
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delay &= (1 << phase->width) - 1;
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if (!delay)
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return 180;
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/* Get our parent clock, it's the one that can adjust its rate */
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parent = clk_hw_get_parent(hw);
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if (!parent)
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return -EINVAL;
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/* And its rate */
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parent_rate = clk_hw_get_rate(parent);
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if (!parent_rate)
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return -EINVAL;
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/* Now, get our parent's parent (most likely some PLL) */
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grandparent = clk_hw_get_parent(parent);
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if (!grandparent)
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return -EINVAL;
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/* And its rate */
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grandparent_rate = clk_hw_get_rate(grandparent);
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if (!grandparent_rate)
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return -EINVAL;
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/* Get our parent clock divider */
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parent_div = grandparent_rate / parent_rate;
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step = DIV_ROUND_CLOSEST(360, parent_div);
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return delay * step;
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}
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static int ccu_phase_set_phase(struct clk_hw *hw, int degrees)
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{
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struct ccu_phase *phase = hw_to_ccu_phase(hw);
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struct clk_hw *parent, *grandparent;
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unsigned int parent_rate, grandparent_rate;
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unsigned long flags;
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u32 reg;
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u8 delay;
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/* Get our parent clock, it's the one that can adjust its rate */
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parent = clk_hw_get_parent(hw);
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if (!parent)
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return -EINVAL;
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/* And its rate */
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parent_rate = clk_hw_get_rate(parent);
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if (!parent_rate)
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return -EINVAL;
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/* Now, get our parent's parent (most likely some PLL) */
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grandparent = clk_hw_get_parent(parent);
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if (!grandparent)
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return -EINVAL;
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/* And its rate */
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grandparent_rate = clk_hw_get_rate(grandparent);
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if (!grandparent_rate)
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return -EINVAL;
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if (degrees != 180) {
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u16 step, parent_div;
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/* Get our parent divider */
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parent_div = grandparent_rate / parent_rate;
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/*
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* We can only outphase the clocks by multiple of the
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* PLL's period.
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*
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* Since our parent clock is only a divider, and the
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* formula to get the outphasing in degrees is deg =
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* 360 * delta / period
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*
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* If we simplify this formula, we can see that the
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* only thing that we're concerned about is the number
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* of period we want to outphase our clock from, and
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* the divider set by our parent clock.
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*/
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step = DIV_ROUND_CLOSEST(360, parent_div);
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delay = DIV_ROUND_CLOSEST(degrees, step);
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} else {
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delay = 0;
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}
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spin_lock_irqsave(phase->common.lock, flags);
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reg = readl(phase->common.base + phase->common.reg);
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reg &= ~GENMASK(phase->width + phase->shift - 1, phase->shift);
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writel(reg | (delay << phase->shift),
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phase->common.base + phase->common.reg);
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spin_unlock_irqrestore(phase->common.lock, flags);
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return 0;
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}
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const struct clk_ops ccu_phase_ops = {
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.get_phase = ccu_phase_get_phase,
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.set_phase = ccu_phase_set_phase,
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};
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EXPORT_SYMBOL_NS_GPL(ccu_phase_ops, SUNXI_CCU);
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