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When MIPS KVM needs to write a TLB entry for the guest it reads the CP0_Random register, uses it to generate the CP_Index, and writes the TLB entry using the TLBWI instruction (tlb_write_indexed()). However there's an instruction for that, TLBWR (tlb_write_random()) so use that instead. This happens to also fix an issue with Ingenic XBurst cores where the same TLB entry is replaced each time preventing forward progress on stores due to alternating between TLB load misses for the instruction fetch and TLB store misses. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@kernel.org> Cc: kvm@vger.kernel.org Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> |
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| .. | ||
| 00README.txt | ||
| Kconfig | ||
| kvm_cb.c | ||
| kvm_locore.S | ||
| kvm_mips.c | ||
| kvm_mips_comm.h | ||
| kvm_mips_commpage.c | ||
| kvm_mips_dyntrans.c | ||
| kvm_mips_emul.c | ||
| kvm_mips_int.c | ||
| kvm_mips_int.h | ||
| kvm_mips_opcode.h | ||
| kvm_mips_stats.c | ||
| kvm_tlb.c | ||
| kvm_trap_emul.c | ||
| Makefile | ||
| trace.h | ||