Vineet Gupta b5ddb6d547 ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC ... PAE40 confiuration in hardware extends some of the address registers for TLB/cache ops to 2 words. So far kernel was NOT setting the higher word if feature was not enabled in software which is wrong. Those need to be set to 0 in such case. Normally this would be done in the cache flush / tlb ops, however since these registers only exist conditionally, this would have to be conditional to a flag being set on boot which is expensive/ugly - specially for the more common case of PAE exists but not in use. Optimize that by zero'ing them once at boot - nobody will write to them afterwards Cc: stable@vger.kernel.org #4.4+ Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2017-08-04 13:56:35 +05:30
..
cache.c	ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC	2017-08-04 13:56:35 +05:30
dma.c	ARC: dma: implement dma_unmap_page and sg variant	2017-08-04 13:56:33 +05:30
extable.c	ARC: uaccess: enable INLINE_COPY_{TO,FROM}_USER ...	2017-03-30 00:07:48 -04:00
fault.c	sched/headers: Prepare for new header dependencies before moving code to <linux/sched/signal.h>	2017-03-02 08:42:29 +01:00
highmem.c	ARC: export kmap	2016-08-19 10:45:29 -07:00
init.c	ARCv2: IOC: Use actual memory size to setup aperture size	2017-01-18 14:52:43 -08:00
ioremap.c	ARCv2: Support dynamic peripheral address space in HS38 rel 3.0 cores	2016-09-30 14:48:17 -07:00
Makefile	ARC: mm: HIGHMEM: kmap API implementation	2015-10-28 19:49:04 +05:30
mmap.c	mm: larger stack guard gap, between vmas	2017-06-19 21:50:20 +08:00
tlb.c	ARCv2: PAE40: set MSB even if !CONFIG_ARC_HAS_PAE40 but PAE exists in SoC	2017-08-04 13:56:35 +05:30
tlbex.S	ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...	2016-10-28 10:10:28 -07:00