Markos Chandras b5ad2c2193 MIPS: mm: scache: Add secondary cache support for MIPS R6 cores ... The secondary cache initialization and configuration code is processor specific so we need to handle MIPS R6 cores as well. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>		2015-02-17 15:37:31 +00:00
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c-octeon.c
c-r3k.c
c-r4k.c	MIPS: mm: scache: Add secondary cache support for MIPS R6 cores	2015-02-17 15:37:31 +00:00
c-tx39.c
cache.c	MIPS: Remove race window in page fault handling	2014-08-19 13:31:09 +02:00
cerr-sb1.c
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c	MIPS: DMA: Explain the lack of special handling for R14000/R16000.	2014-11-24 07:45:08 +01:00
extable.c
fault.c	MIPS: mm: Add debug information for userland SIGSEGV signals.	2015-02-16 10:55:26 +01:00
gup.c	kernel: Provide READ_ONCE and ASSIGN_ONCE	2014-12-20 16:48:59 -08:00
highmem.c
hugetlbpage.c
init.c	MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT	2014-11-24 22:46:44 +01:00
ioremap.c	MIPS: Replace use of phys_t with phys_addr_t.	2014-11-24 22:47:31 +01:00
Makefile	MIPS: mm: Only build one microassembler that is suitable	2014-11-24 07:45:36 +01:00
mmap.c
page-funcs.S
page.c	MIPS: mm: page: Add MIPS R6 support	2015-02-17 15:37:30 +00:00
pgtable-32.c
pgtable-64.c
sc-ip22.c
sc-mips.c	MIPS: mm: scache: Add secondary cache support for MIPS R6 cores	2015-02-17 15:37:31 +00:00
sc-r5k.c	MIPS: Remove useless parentheses	2014-11-24 07:44:49 +01:00
sc-rm7k.c
tlb-funcs.S
tlb-r3k.c	MIPS: Remove incorrect NULL check in local_flush_tlb_page()	2014-07-30 20:59:43 +02:00
tlb-r4k.c	MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT	2014-11-24 22:46:44 +01:00
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: mm: tlbex: Use cpu_has_mips_r2_exec_hazard for the EHB instruction	2015-02-17 15:37:30 +00:00
uasm-micromips.c	MIPS: uasm: Add SLT uasm instruction	2014-06-26 10:48:19 +01:00
uasm-mips.c	MIPS: mm: Add MIPS R6 instruction encodings	2015-02-16 14:02:50 +00:00
uasm.c	MIPS: mm: uasm: Add signed 9-bit immediate related macros	2015-02-16 10:01:25 +00:00