mirror of
https://github.com/torvalds/linux
synced 2024-10-14 15:29:13 +00:00
4527e83780
- Core and platform-MSI
The core changes have been adopted from previous work which converted
ARM[64] to the new per device MSI domain model, which was merged to
support multiple MSI domain per device. The ARM[64] changes are being
worked on too, but have not been ready yet. The core and platform-MSI
changes have been split out to not hold up RISC-V and to avoid that
RISC-V builds on the scheduled for removal interfaces.
The core support provides new interfaces to handle wire to MSI bridges
in a straight forward way and introduces new platform-MSI interfaces
which are built on top of the per device MSI domain model.
Once ARM[64] is converted over the old platform-MSI interfaces and the
related ugliness in the MSI core code will be removed.
- Drivers:
- Add a new driver for the Andes hart-level interrupt controller
- Rework the SiFive PLIC driver to prepare for MSI suport
- Expand the RISC-V INTC driver to support the new RISC-V AIA
controller which provides the basis for MSI on RISC-V
- A few fixup for the fallout of the core changes.
The actual MSI parts for RISC-V were finalized late and have been
post-poned for the next merge window.
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEEQp8+kY+LLUocC4bMphj1TA10mKEFAmXt7MsTHHRnbHhAbGlu
dXRyb25peC5kZQAKCRCmGPVMDXSYofrMD/9Dag12ttmbE2uqzTzlTxc7RHC2MX5n
VJLt84FNNwGPA4r7WLOOqHrfuvfoGjuWT9pYMrVaXCglRG1CMvL10kHMB2f28UWv
Qpc5PzbJwpD6tqyfRSFHMoJp63DAI8IpS7J3I8bqnRD8+0PwYn3jMA1+iMZkH0B7
8uO3mxlFhQ7BFvIAeMEAhR0szuAfvXqEtpi1iTgQTrQ4Je4Rf1pmLjEe2rkwDvF4
p3SAmPIh4+F3IjO7vNsVkQ2yOarTP2cpSns6JmO8mrobLIVX7ZCQ6uVaVCfBhxfx
WttuJO6Bmh/I15yDe/waH6q9ym+0VBwYRWi5lonMpViGdq4/D2WVnY1mNeLRIfjl
X65aMWE1+bhiqyIIUfc24hacf0UgBIlMEW4kJ31VmQzb+OyLDXw+UvzWg1dO6XdA
3L6j1nRgHk0ea5yFyH6SfH/mrfeyqHuwHqo17KFyHxD3jM2H1RRMplpbwXiOIepp
KJJ/O06eMEzHqzn4B8GCT2EvX6L2ehgoWbLeEDNLQh/3LwA9OdcBzPr6gsweEl0U
Q7szJgUWZHeMr39F2rnt0GmvkEuu6muEp/nQzfnohjoYZ0PhpMLSq++4Gi+Ko3fz
2IyecJ+tlbSfyM5//8AdNnOSpsTG3f8u6B/WwhGp5lIDwMnMzCssgfQmRnc3Uyv5
kU3pdMjURJaTUA==
=7aXj
-----END PGP SIGNATURE-----
Merge tag 'irq-msi-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull MSI updates from Thomas Gleixner:
"Updates for the MSI interrupt subsystem and initial RISC-V MSI
support.
The core changes have been adopted from previous work which converted
ARM[64] to the new per device MSI domain model, which was merged to
support multiple MSI domain per device. The ARM[64] changes are being
worked on too, but have not been ready yet. The core and platform-MSI
changes have been split out to not hold up RISC-V and to avoid that
RISC-V builds on the scheduled for removal interfaces.
The core support provides new interfaces to handle wire to MSI bridges
in a straight forward way and introduces new platform-MSI interfaces
which are built on top of the per device MSI domain model.
Once ARM[64] is converted over the old platform-MSI interfaces and the
related ugliness in the MSI core code will be removed.
The actual MSI parts for RISC-V were finalized late and have been
post-poned for the next merge window.
Drivers:
- Add a new driver for the Andes hart-level interrupt controller
- Rework the SiFive PLIC driver to prepare for MSI suport
- Expand the RISC-V INTC driver to support the new RISC-V AIA
controller which provides the basis for MSI on RISC-V
- A few fixup for the fallout of the core changes"
* tag 'irq-msi-2024-03-10' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (29 commits)
irqchip/riscv-intc: Fix low-level interrupt handler setup for AIA
x86/apic/msi: Use DOMAIN_BUS_GENERIC_MSI for HPET/IO-APIC domain search
genirq/matrix: Dynamic bitmap allocation
irqchip/riscv-intc: Add support for RISC-V AIA
irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore
irqchip/sifive-plic: Parse number of interrupts and contexts early in plic_probe()
irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure
irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode
irqchip/sifive-plic: Use devm_xyz() for managed allocation
irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz()
irqchip/sifive-plic: Convert PLIC driver into a platform driver
irqchip/riscv-intc: Introduce Andes hart-level interrupt controller
irqchip/riscv-intc: Allow large non-standard interrupt number
genirq/irqdomain: Don't call ops->select for DOMAIN_BUS_ANY tokens
irqchip/imx-intmux: Handle pure domain searches correctly
genirq/msi: Provide MSI_FLAG_PARENT_PM_DEV
genirq/irqdomain: Reroute device MSI create_mapping
genirq/msi: Provide allocation/free functions for "wired" MSI interrupts
genirq/msi: Optionally use dev->fwnode for device domain
genirq/msi: Provide DOMAIN_BUS_WIRED_TO_MSI
...
|
||
|---|---|---|
| .. | ||
| alphascale_asm9260-icoll.h | ||
| exynos-combiner.c | ||
| irq-al-fic.c | ||
| irq-alpine-msi.c | ||
| irq-apple-aic.c | ||
| irq-armada-370-xp.c | ||
| irq-aspeed-i2c-ic.c | ||
| irq-aspeed-scu-ic.c | ||
| irq-aspeed-vic.c | ||
| irq-ath79-cpu.c | ||
| irq-ath79-misc.c | ||
| irq-atmel-aic-common.c | ||
| irq-atmel-aic-common.h | ||
| irq-atmel-aic.c | ||
| irq-atmel-aic5.c | ||
| irq-bcm2835.c | ||
| irq-bcm2836.c | ||
| irq-bcm6345-l1.c | ||
| irq-bcm7038-l1.c | ||
| irq-bcm7120-l2.c | ||
| irq-brcmstb-l2.c | ||
| irq-clps711x.c | ||
| irq-crossbar.c | ||
| irq-csky-apb-intc.c | ||
| irq-csky-mpintc.c | ||
| irq-davinci-cp-intc.c | ||
| irq-digicolor.c | ||
| irq-dw-apb-ictl.c | ||
| irq-ftintc010.c | ||
| irq-gic-common.c | ||
| irq-gic-common.h | ||
| irq-gic-pm.c | ||
| irq-gic-realview.c | ||
| irq-gic-v2m.c | ||
| irq-gic-v3-its-fsl-mc-msi.c | ||
| irq-gic-v3-its-pci-msi.c | ||
| irq-gic-v3-its-platform-msi.c | ||
| irq-gic-v3-its.c | ||
| irq-gic-v3-mbi.c | ||
| irq-gic-v3.c | ||
| irq-gic-v4.c | ||
| irq-gic.c | ||
| irq-goldfish-pic.c | ||
| irq-hip04.c | ||
| irq-i8259.c | ||
| irq-idt3243x.c | ||
| irq-imgpdc.c | ||
| irq-imx-gpcv2.c | ||
| irq-imx-intmux.c | ||
| irq-imx-irqsteer.c | ||
| irq-imx-mu-msi.c | ||
| irq-ingenic-tcu.c | ||
| irq-ingenic.c | ||
| irq-ixp4xx.c | ||
| irq-jcore-aic.c | ||
| irq-keystone.c | ||
| irq-loongarch-cpu.c | ||
| irq-loongson-eiointc.c | ||
| irq-loongson-htpic.c | ||
| irq-loongson-htvec.c | ||
| irq-loongson-liointc.c | ||
| irq-loongson-pch-lpc.c | ||
| irq-loongson-pch-msi.c | ||
| irq-loongson-pch-pic.c | ||
| irq-lpc32xx.c | ||
| irq-ls-extirq.c | ||
| irq-ls-scfg-msi.c | ||
| irq-ls1x.c | ||
| irq-madera.c | ||
| irq-mbigen.c | ||
| irq-mchp-eic.c | ||
| irq-meson-gpio.c | ||
| irq-mips-cpu.c | ||
| irq-mips-gic.c | ||
| irq-mmp.c | ||
| irq-mscc-ocelot.c | ||
| irq-mst-intc.c | ||
| irq-mtk-cirq.c | ||
| irq-mtk-sysirq.c | ||
| irq-mvebu-gicp.c | ||
| irq-mvebu-icu.c | ||
| irq-mvebu-odmi.c | ||
| irq-mvebu-pic.c | ||
| irq-mvebu-sei.c | ||
| irq-mxs.c | ||
| irq-nvic.c | ||
| irq-omap-intc.c | ||
| irq-ompic.c | ||
| irq-or1k-pic.c | ||
| irq-orion.c | ||
| irq-owl-sirq.c | ||
| irq-partition-percpu.c | ||
| irq-pic32-evic.c | ||
| irq-pruss-intc.c | ||
| irq-qcom-mpm.c | ||
| irq-rda-intc.c | ||
| irq-realtek-rtl.c | ||
| irq-renesas-intc-irqpin.c | ||
| irq-renesas-irqc.c | ||
| irq-renesas-rza1.c | ||
| irq-renesas-rzg2l.c | ||
| irq-riscv-intc.c | ||
| irq-sa11x0.c | ||
| irq-sifive-plic.c | ||
| irq-sl28cpld.c | ||
| irq-sni-exiu.c | ||
| irq-sp7021-intc.c | ||
| irq-st.c | ||
| irq-starfive-jh8100-intc.c | ||
| irq-stm32-exti.c | ||
| irq-sun4i.c | ||
| irq-sun6i-r.c | ||
| irq-sunxi-nmi.c | ||
| irq-tb10x.c | ||
| irq-tegra.c | ||
| irq-ti-sci-inta.c | ||
| irq-ti-sci-intr.c | ||
| irq-ts4800.c | ||
| irq-uniphier-aidet.c | ||
| irq-versatile-fpga.c | ||
| irq-vf610-mscm-ir.c | ||
| irq-vic.c | ||
| irq-vt8500.c | ||
| irq-wpcm450-aic.c | ||
| irq-xilinx-intc.c | ||
| irq-xtensa-mx.c | ||
| irq-xtensa-pic.c | ||
| irq-zevio.c | ||
| irqchip.c | ||
| Kconfig | ||
| Makefile | ||
| qcom-irq-combiner.c | ||
| qcom-pdc.c | ||
| spear-shirq.c | ||