mirror of
https://github.com/torvalds/linux
synced 2024-10-01 08:50:11 +00:00
![]() For the original tuning code, delay value is set to SD Bus Clock Delay Register (SD_CLK_DELAY_SETTING) as (val | (Val << 7) | (val << 16)), which means CLK_DELAY_IN1, CLK_DELAY_IN2 and CLK_DELAY_OUT are the same and with 128 steps. This is doubtful. In CSR design specification documents CS-304575-DR-3H, this issue is clarified, the delay[13:0] in SD_CLK_DELAY_SETTING is simplied to the concatenation of {CLK_DELAY_IN2, CLK_DELAY_IN1}. Besides, for CMD19 tuning, no need to set CLK_DELAY_OUT([22,16] of SD_CLK_DELAY_SETTING). Signed-off-by: weijun yang <york.yang@csr.com> Signed-off-by: Barry Song <baohua.song@csr.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> |
||
---|---|---|
.. | ||
card | ||
core | ||
host | ||
Kconfig | ||
Makefile |