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This pull request contains various cleanup and minor changes to core Tegra code: * Tegra clocksource driver is moved to drivers/clocksource. * Various typos, warning cleanup, statics cleanup, section mismatch fixes, etc. * Various small fixes/cleanups for CPU/hotplug/SMP code. This pull request is based on a merge of v3.8-rc3 and at least part of arm-soc's timer/cleanup branch. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJRCYapAAoJEMzrak5tbycxp0kQAKYlx2XFf8lgv+V/zDRmzXvr 7dW1bByqBIqrhoOxYM+WGLtcVT+n23MbwXUsbRp2hKGzNSD4+VG05bBrEutfjdnf bDiJeLkA+95e1Slx/BPzE7SYoOuNxR0YuVuFD8JkL+ykD0NtoJsoS3eUZB+7/bQ7 Ld9GscUndy7GDoo04Dr72OhVwESVHqahvSPWc5xPsE8ua6ZTiTg+x4UgzrbUpHoQ CN3ABkJfeYr2pERSiZDJwuyWTDx/d9MHpcK2JNVht0AayIcXRUKUwKiJiUPtDsA1 RQvk3UB0iwA6lWnr+ApJtDpNQOfx7MbYY/VIRJ2krmZiOGl3fewMkNUhpTcs+wBJ HumdCb9bDha+o8hYAthibhBurENP6ydwEpkinIANsj4HIQYwGNVaFBZaN9gbrtKs 8jgQsrjiZSwFSpyyMyuNy1mg2M3TI0WExEpTQx0KG41g49CvhlhrPpR6HfbjjpDb 9/Pw5J7nMrSNNjxYKMUKfBtnrceAaZ96riFZfDJmc1WTnv0OCfzfRfTkc3+6peE7 ItNHwux5p6M1DfPvMEZA9qwKbLSdZCGtKQ0vElJjQeqU+tXNtb2H9AEOYoZkTUSQ 7rdkJM9nDLWtXjb1vql8XEYsxD28nLGyOWnE5yOrM/qZ28sgfY7bmt9R0NGaoWRO moveNklG/UDcANbi2LuU =H2vV -----END PGP SIGNATURE----- Merge tag 'tegra-for-3.9-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/cleanup From Stephen Warren: ARM: tegra: cleanup This pull request contains various cleanup and minor changes to core Tegra code: * Tegra clocksource driver is moved to drivers/clocksource. * Various typos, warning cleanup, statics cleanup, section mismatch fixes, etc. * Various small fixes/cleanups for CPU/hotplug/SMP code. This pull request is based on a merge of v3.8-rc3 and at least part of arm-soc's timer/cleanup branch. * tag 'tegra-for-3.9-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: ARM: tegra: fix compile error when disable CPU_IDLE ARM: tegra30: make the wait time of CPU power up to proportional to HZ ARM: tegra: make device can run on UP ARM: tegra: clean up the CPUINIT section ARM: tegra: moving the clock gating procedure to tegra_cpu_kill ARM: tegra: update the cache maintenance order for CPU shutdown ARM: tegra30: fix power up sequence for boot_secondary ARM: tegra: cpufreq: move clk_get/put out of function tegra_cpu_init/exit ARM: tegra: fix Kconfig warnings when !SMP ARM: tegra: Make variables static clocksource: tegra: cosmetic: Fix error message ARM: tegra: move timer.c to drivers/clocksource/ Signed-off-by: Olof Johansson <olof@lixom.net> Trivial conflicts: arch/arm/mach-tegra/board-dt-tegra20.c arch/arm/mach-tegra/board-dt-tegra30.c drivers/clocksource/Makefile
121 lines
4.5 KiB
C
121 lines
4.5 KiB
C
/*
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* arch/arm/mach-tegra/board-dt-tegra30.c
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*
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* NVIDIA Tegra30 device tree board support
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*
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* Copyright (C) 2011 NVIDIA Corporation
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*
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* Derived from:
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*
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* arch/arm/mach-tegra/board-dt-tegra20.c
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*
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* Copyright (C) 2010 Secret Lab Technologies, Ltd.
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* Copyright (C) 2010 Google, Inc.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/clocksource.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <asm/mach/arch.h>
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#include "board.h"
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#include "clock.h"
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#include "common.h"
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#include "iomap.h"
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static struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000200, "sdhci-tegra.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000400, "sdhci-tegra.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000600, "sdhci-tegra.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C000, "tegra-i2c.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C400, "tegra-i2c.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
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OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
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{}
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};
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static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
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/* name parent rate enabled */
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{ "uarta", "pll_p", 408000000, true },
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{ "pll_a", "pll_p_out1", 564480000, true },
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{ "pll_a_out0", "pll_a", 11289600, true },
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{ "extern1", "pll_a_out0", 0, true },
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{ "clk_out_1", "extern1", 0, true },
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{ "blink", "clk_32k", 32768, true },
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{ "i2s0", "pll_a_out0", 11289600, false},
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{ "i2s1", "pll_a_out0", 11289600, false},
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{ "i2s2", "pll_a_out0", 11289600, false},
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{ "i2s3", "pll_a_out0", 11289600, false},
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{ "i2s4", "pll_a_out0", 11289600, false},
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{ "sdmmc1", "pll_p", 48000000, false},
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{ "sdmmc3", "pll_p", 48000000, false},
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{ "sdmmc4", "pll_p", 48000000, false},
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{ "sbc1", "pll_p", 100000000, false},
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{ "sbc2", "pll_p", 100000000, false},
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{ "sbc3", "pll_p", 100000000, false},
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{ "sbc4", "pll_p", 100000000, false},
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{ "sbc5", "pll_p", 100000000, false},
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{ "sbc6", "pll_p", 100000000, false},
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{ "host1x", "pll_c", 150000000, false},
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{ "disp1", "pll_p", 600000000, false},
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{ "disp2", "pll_p", 600000000, false},
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{ NULL, NULL, 0, 0},
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};
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static void __init tegra30_dt_init(void)
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{
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tegra_clk_init_from_table(tegra_dt_clk_init_table);
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of_platform_populate(NULL, of_default_bus_match_table,
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tegra30_auxdata_lookup, NULL);
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}
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static const char *tegra30_dt_board_compat[] = {
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"nvidia,tegra30",
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NULL
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};
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DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
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.smp = smp_ops(tegra_smp_ops),
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.map_io = tegra_map_common_io,
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.init_early = tegra30_init_early,
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.init_irq = tegra_dt_init_irq,
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.init_time = clocksource_of_init,
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.init_machine = tegra30_dt_init,
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.init_late = tegra_init_late,
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.restart = tegra_assert_system_reset,
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.dt_compat = tegra30_dt_board_compat,
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MACHINE_END
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