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It's not a good idea to use "ssm psr.ic | psr.i" to simultaneously enable interrupts and interrupt state collection, the two bits can take effect asynchronously, so it is possible for an interrupt to be serviced while psr.ic is still zero. Signed-off-by: Tony Luck <tony.luck@intel.com>
56 lines
1.1 KiB
ArmAsm
56 lines
1.1 KiB
ArmAsm
/*
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* File: mca_drv_asm.S
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* Purpose: Assembly portion of Generic MCA handling
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*
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* Copyright (C) 2004 FUJITSU LIMITED
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* Copyright (C) Hidetoshi Seto (seto.hidetoshi@jp.fujitsu.com)
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*/
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#include <linux/threads.h>
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#include <asm/asmmacro.h>
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#include <asm/processor.h>
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#include <asm/ptrace.h>
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GLOBAL_ENTRY(mca_handler_bhhook)
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invala // clear RSE ?
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cover
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;;
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clrrrb
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;;
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alloc r16=ar.pfs,0,2,3,0 // make a new frame
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mov ar.rsc=0
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mov r13=IA64_KR(CURRENT) // current task pointer
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;;
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mov r2=r13
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;;
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addl r22=IA64_RBS_OFFSET,r2
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;;
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mov ar.bspstore=r22
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addl sp=IA64_STK_OFFSET-IA64_PT_REGS_SIZE,r2
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;;
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adds r2=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
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;;
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st1 [r2]=r0 // clear current->thread.on_ustack flag
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mov loc0=r16
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movl loc1=mca_handler_bh // recovery C function
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;;
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mov out0=r8 // poisoned address
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mov out1=r9 // iip
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mov out2=r10 // psr
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mov b6=loc1
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;;
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mov loc1=rp
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ssm psr.ic
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;;
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srlz.i
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;;
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ssm psr.i
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br.call.sptk.many rp=b6 // does not return ...
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;;
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mov ar.pfs=loc0
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mov rp=loc1
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;;
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mov r8=r0
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br.ret.sptk.many rp
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END(mca_handler_bhhook)
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