Atish Patra a9ac6c3752 RISC-V: KVM: Implement trap & emulate for hpmcounters ... As the KVM guests only see the virtual PMU counters, all hpmcounter access should trap and KVM emulates the read access on behalf of guests. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>		2023-02-07 20:36:01 +05:30
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asm	RISC-V: KVM: Implement trap & emulate for hpmcounters	2023-02-07 20:36:01 +05:30
uapi/asm	KVM/riscv changes for 6.2	2022-12-21 18:52:15 -08:00