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The SDMMC controllers have extra bits in the clock source register that adjust the delay between the clock and data to compenstate for delays on the PCB. The values need to be set from the clock code so the clock can be locked during the read-modify-write on the clock source register. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
32 lines
869 B
C
32 lines
869 B
C
/*
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* arch/arm/mach-tegra/include/mach/clk.h
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*
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* Copyright (C) 2010 Google, Inc.
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*
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* Author:
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* Erik Gilling <konkers@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __MACH_CLK_H
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#define __MACH_CLK_H
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struct clk;
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void tegra_periph_reset_deassert(struct clk *c);
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void tegra_periph_reset_assert(struct clk *c);
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unsigned long clk_get_rate_all_locked(struct clk *c);
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void tegra_sdmmc_tap_delay(struct clk *c, int delay);
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#endif
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