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04dc78b419
This driver uses the same area for MTRR as for the ioremap().
Convert the driver from using the x86 specific MTRR code to
the architecture agnostic arch_phys_wc_add(). arch_phys_wc_add()
will avoid MTRR if write-combining is available, in order to
take advantage of that also ensure the ioremap'd area is requested
as write-combining.
There are a few motivations for this:
a) Take advantage of PAT when available
b) Help bury MTRR code away, MTRR is architecture specific and on
x86 its replaced by PAT
c) Help with the goal of eventually using _PAGE_CACHE_UC over
_PAGE_CACHE_UC_MINUS on x86 on ioremap_nocache() (see commit
de33c442e titled "x86 PAT: fix performance drop for glx,
use UC minus for ioremap(), ioremap_nocache() and
pci_mmap_page_range()")
The conversion done is expressed by the following Coccinelle
SmPL patch, it additionally required manual intervention to
address all the #ifdery and removal of redundant things which
arch_phys_wc_add() already addresses such as verbose message
about when MTRR fails and doing nothing when we didn't get
an MTRR.
@ mtrr_found @
expression index, base, size;
@@
-index = mtrr_add(base, size, MTRR_TYPE_WRCOMB, 1);
+index = arch_phys_wc_add(base, size);
@ mtrr_rm depends on mtrr_found @
expression mtrr_found.index, mtrr_found.base, mtrr_found.size;
@@
-mtrr_del(index, base, size);
+arch_phys_wc_del(index);
@ mtrr_rm_zero_arg depends on mtrr_found @
expression mtrr_found.index;
@@
-mtrr_del(index, 0, 0);
+arch_phys_wc_del(index);
@ mtrr_rm_fb_info depends on mtrr_found @
struct fb_info *info;
expression mtrr_found.index;
@@
-mtrr_del(index, info->fix.smem_start, info->fix.smem_len);
+arch_phys_wc_del(index);
@ ioremap_replace_nocache depends on mtrr_found @
struct fb_info *info;
expression base, size;
@@
-info->screen_base = ioremap_nocache(base, size);
+info->screen_base = ioremap_wc(base, size);
@ ioremap_replace_default depends on mtrr_found @
struct fb_info *info;
expression base, size;
@@
-info->screen_base = ioremap(base, size);
+info->screen_base = ioremap_wc(base, size);
Generated-by: Coccinelle SmPL
Cc: Antonino Daplas <adaplas@gmail.com>
Cc: Suresh Siddha <sbsiddha@gmail.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Juergen Gross <jgross@suse.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Antonino Daplas <adaplas@gmail.com>
Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-fbdev@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
75 lines
1.8 KiB
C
75 lines
1.8 KiB
C
#ifndef __RIVAFB_H
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#define __RIVAFB_H
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#include <linux/fb.h>
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#include <video/vga.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include "riva_hw.h"
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/* GGI compatibility macros */
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#define NUM_SEQ_REGS 0x05
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#define NUM_CRT_REGS 0x41
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#define NUM_GRC_REGS 0x09
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#define NUM_ATC_REGS 0x15
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/* I2C */
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#define DDC_SCL_READ_MASK (1 << 2)
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#define DDC_SCL_WRITE_MASK (1 << 5)
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#define DDC_SDA_READ_MASK (1 << 3)
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#define DDC_SDA_WRITE_MASK (1 << 4)
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/* holds the state of the VGA core and extended Riva hw state from riva_hw.c.
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* From KGI originally. */
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struct riva_regs {
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u8 attr[NUM_ATC_REGS];
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u8 crtc[NUM_CRT_REGS];
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u8 gra[NUM_GRC_REGS];
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u8 seq[NUM_SEQ_REGS];
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u8 misc_output;
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RIVA_HW_STATE ext;
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};
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struct riva_par;
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struct riva_i2c_chan {
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struct riva_par *par;
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unsigned long ddc_base;
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struct i2c_adapter adapter;
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struct i2c_algo_bit_data algo;
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};
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struct riva_par {
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RIVA_HW_INST riva; /* interface to riva_hw.c */
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u32 pseudo_palette[16]; /* default palette */
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u32 palette[16]; /* for Riva128 */
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u8 __iomem *ctrl_base; /* virtual control register base addr */
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unsigned dclk_max; /* max DCLK */
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struct riva_regs initial_state; /* initial startup video mode */
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struct riva_regs current_state;
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#ifdef CONFIG_X86
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struct vgastate state;
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#endif
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struct mutex open_lock;
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unsigned int ref_count;
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unsigned char *EDID;
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unsigned int Chipset;
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int forceCRTC;
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Bool SecondCRTC;
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int FlatPanel;
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struct pci_dev *pdev;
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int cursor_reset;
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int wc_cookie;
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struct riva_i2c_chan chan[3];
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};
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void riva_common_setup(struct riva_par *);
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unsigned long riva_get_memlen(struct riva_par *);
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unsigned long riva_get_maxdclk(struct riva_par *);
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void riva_delete_i2c_busses(struct riva_par *par);
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void riva_create_i2c_busses(struct riva_par *par);
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int riva_probe_i2c_connector(struct riva_par *par, int conn, u8 **out_edid);
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#endif /* __RIVAFB_H */
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