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![Linus Walleij](/assets/img/avatar_default.png)
As we want gpio_chip .get() calls to be able to return negative error codes and propagate to drivers, we need to go over all drivers and make sure their return values are clamped to [0,1]. We do this by using the ret = !!(val) design pattern. Cc: Anatolij Gustschin <agust@denx.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
216 lines
5.2 KiB
C
216 lines
5.2 KiB
C
/*
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* PPC4xx gpio driver
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*
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* Copyright (c) 2008 Harris Corporation
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* Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
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* Copyright (c) MontaVista Software, Inc. 2008.
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*
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* Author: Steve Falco <sfalco@harris.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#define GPIO_MASK(gpio) (0x80000000 >> (gpio))
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#define GPIO_MASK2(gpio) (0xc0000000 >> ((gpio) * 2))
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/* Physical GPIO register layout */
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struct ppc4xx_gpio {
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__be32 or;
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__be32 tcr;
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__be32 osrl;
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__be32 osrh;
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__be32 tsrl;
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__be32 tsrh;
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__be32 odr;
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__be32 ir;
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__be32 rr1;
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__be32 rr2;
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__be32 rr3;
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__be32 reserved1;
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__be32 isr1l;
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__be32 isr1h;
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__be32 isr2l;
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__be32 isr2h;
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__be32 isr3l;
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__be32 isr3h;
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};
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struct ppc4xx_gpio_chip {
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struct of_mm_gpio_chip mm_gc;
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spinlock_t lock;
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};
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/*
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* GPIO LIB API implementation for GPIOs
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*
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* There are a maximum of 32 gpios in each gpio controller.
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*/
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static inline struct ppc4xx_gpio_chip *
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to_ppc4xx_gpiochip(struct of_mm_gpio_chip *mm_gc)
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{
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return container_of(mm_gc, struct ppc4xx_gpio_chip, mm_gc);
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}
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static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
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return !!(in_be32(®s->ir) & GPIO_MASK(gpio));
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}
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static inline void
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__ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
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if (val)
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setbits32(®s->or, GPIO_MASK(gpio));
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else
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clrbits32(®s->or, GPIO_MASK(gpio));
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}
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static void
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ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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__ppc4xx_gpio_set(gc, gpio, val);
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spin_unlock_irqrestore(&chip->lock, flags);
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pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
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}
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static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
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struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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/* Disable open-drain function */
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clrbits32(®s->odr, GPIO_MASK(gpio));
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/* Float the pin */
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clrbits32(®s->tcr, GPIO_MASK(gpio));
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/* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
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if (gpio < 16) {
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clrbits32(®s->osrl, GPIO_MASK2(gpio));
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clrbits32(®s->tsrl, GPIO_MASK2(gpio));
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} else {
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clrbits32(®s->osrh, GPIO_MASK2(gpio));
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clrbits32(®s->tsrh, GPIO_MASK2(gpio));
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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return 0;
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}
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static int
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ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
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{
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struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
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struct ppc4xx_gpio_chip *chip = to_ppc4xx_gpiochip(mm_gc);
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struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
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unsigned long flags;
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spin_lock_irqsave(&chip->lock, flags);
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/* First set initial value */
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__ppc4xx_gpio_set(gc, gpio, val);
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/* Disable open-drain function */
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clrbits32(®s->odr, GPIO_MASK(gpio));
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/* Drive the pin */
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setbits32(®s->tcr, GPIO_MASK(gpio));
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/* Bits 0-15 use TSRL, bits 16-31 use TSRH */
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if (gpio < 16) {
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clrbits32(®s->osrl, GPIO_MASK2(gpio));
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clrbits32(®s->tsrl, GPIO_MASK2(gpio));
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} else {
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clrbits32(®s->osrh, GPIO_MASK2(gpio));
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clrbits32(®s->tsrh, GPIO_MASK2(gpio));
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}
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spin_unlock_irqrestore(&chip->lock, flags);
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pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
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return 0;
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}
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static int __init ppc4xx_add_gpiochips(void)
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{
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struct device_node *np;
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for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
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int ret;
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struct ppc4xx_gpio_chip *ppc4xx_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct gpio_chip *gc;
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ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
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if (!ppc4xx_gc) {
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ret = -ENOMEM;
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goto err;
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}
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spin_lock_init(&ppc4xx_gc->lock);
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mm_gc = &ppc4xx_gc->mm_gc;
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gc = &mm_gc->gc;
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gc->ngpio = 32;
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gc->direction_input = ppc4xx_gpio_dir_in;
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gc->direction_output = ppc4xx_gpio_dir_out;
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gc->get = ppc4xx_gpio_get;
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gc->set = ppc4xx_gpio_set;
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ret = of_mm_gpiochip_add(np, mm_gc);
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if (ret)
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goto err;
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continue;
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err:
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pr_err("%s: registration failed with status %d\n",
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np->full_name, ret);
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kfree(ppc4xx_gc);
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/* try others anyway */
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}
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return 0;
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}
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arch_initcall(ppc4xx_add_gpiochips);
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