Maciej W. Rozycki a711d43cbb MIPS: Correct mmiowb' barrier for wbflush' platforms ... Redefine `mmiowb' in terms of `iobarrier_w' so that it works correctly for MIPS I platforms, which have no SYNC machine instruction and use a call to `wbflush' instead. This doesn't change the semantics for CONFIG_CPU_CAVIUM_OCTEON, because `iobarrier_w' expands to `wmb', which is ultimately the same as the current arrangement. For MIPS I platforms this not only makes any code that would happen to use `mmiowb' build and run, but it actually enforces the ordering required as well, as `iobarrier_w' has it already covered with the use of `wmb'. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/20863/ Cc: Ralf Baechle <ralf@linux-mips.org>		2018-10-09 10:42:40 -07:00
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asm	MIPS: Correct mmiowb' barrier for wbflush' platforms	2018-10-09 10:42:40 -07:00
uapi/asm	net: Add a new socket option for a future transmit time.	2018-07-04 22:30:27 +09:00