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https://github.com/torvalds/linux
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9600973656
The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Kukjin Kim <kgene@kernel.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Lee Jones <lee@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-rpi-kernel@lists.infradead.org Cc: linux-mediatek@lists.infradead.org Link: http://lkml.kernel.org/r/1430139264-4362-2-git-send-email-k.kozlowski.k@gmail.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
259 lines
6.5 KiB
C
259 lines
6.5 KiB
C
/*
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* arch/arm/mach-vt8500/irq.c
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*
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* This file is copied and modified from the original irq.c provided by
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* Alexey Charkov. Minor changes have been made for Device Tree Support.
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*/
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <asm/irq.h>
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include "irqchip.h"
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#define VT8500_ICPC_IRQ 0x20
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#define VT8500_ICPC_FIQ 0x24
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#define VT8500_ICDC 0x40 /* Destination Control 64*u32 */
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#define VT8500_ICIS 0x80 /* Interrupt status, 16*u32 */
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/* ICPC */
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#define ICPC_MASK 0x3F
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#define ICPC_ROTATE BIT(6)
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/* IC_DCTR */
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#define ICDC_IRQ 0x00
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#define ICDC_FIQ 0x01
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#define ICDC_DSS0 0x02
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#define ICDC_DSS1 0x03
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#define ICDC_DSS2 0x04
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#define ICDC_DSS3 0x05
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#define ICDC_DSS4 0x06
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#define ICDC_DSS5 0x07
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#define VT8500_INT_DISABLE 0
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#define VT8500_INT_ENABLE BIT(3)
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#define VT8500_TRIGGER_HIGH 0
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#define VT8500_TRIGGER_RISING BIT(5)
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#define VT8500_TRIGGER_FALLING BIT(6)
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#define VT8500_EDGE ( VT8500_TRIGGER_RISING \
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| VT8500_TRIGGER_FALLING)
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/* vt8500 has 1 intc, wm8505 and wm8650 have 2 */
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#define VT8500_INTC_MAX 2
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struct vt8500_irq_data {
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void __iomem *base; /* IO Memory base address */
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struct irq_domain *domain; /* Domain for this controller */
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};
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/* Global variable for accessing io-mem addresses */
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static struct vt8500_irq_data intc[VT8500_INTC_MAX];
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static u32 active_cnt = 0;
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static void vt8500_irq_mask(struct irq_data *d)
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{
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struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);
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u8 edge, dctr;
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u32 status;
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edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;
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if (edge) {
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status = readl(stat_reg);
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status |= (1 << (d->hwirq & 0x1f));
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writel(status, stat_reg);
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} else {
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dctr = readb(base + VT8500_ICDC + d->hwirq);
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dctr &= ~VT8500_INT_ENABLE;
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writeb(dctr, base + VT8500_ICDC + d->hwirq);
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}
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}
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static void vt8500_irq_unmask(struct irq_data *d)
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{
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struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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u8 dctr;
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dctr = readb(base + VT8500_ICDC + d->hwirq);
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dctr |= VT8500_INT_ENABLE;
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writeb(dctr, base + VT8500_ICDC + d->hwirq);
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}
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static int vt8500_irq_set_type(struct irq_data *d, unsigned int flow_type)
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{
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struct vt8500_irq_data *priv = d->domain->host_data;
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void __iomem *base = priv->base;
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u8 dctr;
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dctr = readb(base + VT8500_ICDC + d->hwirq);
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dctr &= ~VT8500_EDGE;
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switch (flow_type) {
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case IRQF_TRIGGER_LOW:
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return -EINVAL;
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case IRQF_TRIGGER_HIGH:
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dctr |= VT8500_TRIGGER_HIGH;
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__irq_set_handler_locked(d->irq, handle_level_irq);
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break;
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case IRQF_TRIGGER_FALLING:
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dctr |= VT8500_TRIGGER_FALLING;
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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break;
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case IRQF_TRIGGER_RISING:
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dctr |= VT8500_TRIGGER_RISING;
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__irq_set_handler_locked(d->irq, handle_edge_irq);
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break;
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}
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writeb(dctr, base + VT8500_ICDC + d->hwirq);
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return 0;
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}
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static struct irq_chip vt8500_irq_chip = {
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.name = "vt8500",
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.irq_ack = vt8500_irq_mask,
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.irq_mask = vt8500_irq_mask,
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.irq_unmask = vt8500_irq_unmask,
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.irq_set_type = vt8500_irq_set_type,
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};
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static void __init vt8500_init_irq_hw(void __iomem *base)
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{
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u32 i;
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/* Enable rotating priority for IRQ */
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writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);
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writel(0x00, base + VT8500_ICPC_FIQ);
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/* Disable all interrupts and route them to IRQ */
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for (i = 0; i < 64; i++)
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writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);
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}
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static int vt8500_irq_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &vt8500_irq_chip, handle_level_irq);
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set_irq_flags(virq, IRQF_VALID);
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return 0;
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}
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static const struct irq_domain_ops vt8500_irq_domain_ops = {
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.map = vt8500_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static void __exception_irq_entry vt8500_handle_irq(struct pt_regs *regs)
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{
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u32 stat, i;
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int irqnr;
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void __iomem *base;
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/* Loop through each active controller */
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for (i=0; i<active_cnt; i++) {
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base = intc[i].base;
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irqnr = readl_relaxed(base) & 0x3F;
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/*
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Highest Priority register default = 63, so check that this
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is a real interrupt by checking the status register
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*/
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if (irqnr == 63) {
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stat = readl_relaxed(base + VT8500_ICIS + 4);
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if (!(stat & BIT(31)))
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continue;
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}
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handle_domain_irq(intc[i].domain, irqnr, regs);
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}
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}
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static int __init vt8500_irq_init(struct device_node *node,
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struct device_node *parent)
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{
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int irq, i;
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struct device_node *np = node;
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if (active_cnt == VT8500_INTC_MAX) {
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pr_err("%s: Interrupt controllers > VT8500_INTC_MAX\n",
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__func__);
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goto out;
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}
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intc[active_cnt].base = of_iomap(np, 0);
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intc[active_cnt].domain = irq_domain_add_linear(node, 64,
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&vt8500_irq_domain_ops, &intc[active_cnt]);
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if (!intc[active_cnt].base) {
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pr_err("%s: Unable to map IO memory\n", __func__);
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goto out;
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}
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if (!intc[active_cnt].domain) {
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pr_err("%s: Unable to add irq domain!\n", __func__);
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goto out;
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}
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set_handle_irq(vt8500_handle_irq);
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vt8500_init_irq_hw(intc[active_cnt].base);
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pr_info("vt8500-irq: Added interrupt controller\n");
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active_cnt++;
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/* check if this is a slaved controller */
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if (of_irq_count(np) != 0) {
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/* check that we have the correct number of interrupts */
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if (of_irq_count(np) != 8) {
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pr_err("%s: Incorrect IRQ map for slaved controller\n",
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__func__);
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return -EINVAL;
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}
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for (i = 0; i < 8; i++) {
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irq = irq_of_parse_and_map(np, i);
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enable_irq(irq);
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}
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pr_info("vt8500-irq: Enabled slave->parent interrupts\n");
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}
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out:
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return 0;
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}
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IRQCHIP_DECLARE(vt8500_irq, "via,vt8500-intc", vt8500_irq_init);
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