linux/drivers/parisc
Linus Torvalds a923874198 PCI changes for the v3.12 merge window:
PCI device hotplug
     - Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
     - Assign resources on per-host bridge basis (Yinghai Lu)
 
   MPS (Max Payload Size)
     - Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
     - Add warnings about unsafe MPS settings (Yijing Wang)
     - Simplify interface and messages (Bjorn Helgaas)
 
   SR-IOV
     - Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
     - Update NumVFs register when disabling SR-IOV (Yijing Wang)
 
   Virtualization
     - Add bus and slot reset support (Alex Williamson)
     - Fix ACS (Access Control Services) issues (Alex Williamson)
 
   Miscellaneous
     - Simplify PCIe Capability accessors (Bjorn Helgaas)
     - Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
     - Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
     - Delay enabling bridges until they're needed (Yinghai Lu)
     - Split Designware support into Synopsys and Exynos parts (Jingoo Han)
     - Convert class code to use dev_groups (Greg Kroah-Hartman)
     - Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
     - Fix bridge I/O window alignment (Bjorn Helgaas)
     - Add pci_wait_for_pending_transaction() (Casey Leedom)
     - Use devm_ioremap_resource() in Marvell driver (Tushar Behera)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJSJiBcAAoJEFmIoMA60/r8xJgQAJML7aDmo3ASfabGrfY12fUR
 10Miud/MzlX8/AjPSVW0BodpPMmyQY/Viqd9nBWVm3OR9JSrBp2Q8a3Qge5c0GsE
 dMpO3bJrjOmexaAP3wqEQ/NNyL+iIO7fVQsjHf0uyYTS359Ed0TMWsLQwjAa+h2d
 bB2Ul1AqNiXywCj8Kxnzz52DLnRn1g2YVwp7hACCXyQ+NDVDqhgbxLBnbEFkQqOr
 jAF38xz6DuyVTF+EzIIUDWsOLuo5s0qC3aai36yrVwUuuppBFFX4QRoUOaerZRwe
 2WCSa8jqI5QnOPU0LYIPr24DJa6LKCtuSJXUE5hKZgz70UsNefRkV3F5lzB/YlXt
 t5PYH9B27fEyokh8gGmyytAKkutbm8RH3+99cjNzf/UKuiJgzZE27qi3A+DEpJft
 Igl4WoIC39/fhDSvmpGfd7BWvEkdz86UKdB9f7Wz6+NpWoDLiYiwqkOGuF0bo7zo
 3vH48s5VAR8avyGeSUPGFcP9Bq+Hi936xzZxq+Hrj0hASPTpOMTLD1XCqomONO26
 x6x0ipHRDTh3TixHN7KENqyIJCkY/vlzt4kDnzytZe4TupJX+hlG74fq98hpoEFy
 y2RPiLB8jahPf+fr4cmltqiv6WAhcUcJuGdcAF+Ht4wlrIDELR8e7AKH4Q04B/5O
 I8FCB6bay8mvW6MMSXql
 =uNEk
 -----END PGP SIGNATURE-----

Merge tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas:

  PCI device hotplug:
    - Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
    - Assign resources on per-host bridge basis (Yinghai Lu)

  MPS (Max Payload Size):
    - Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
    - Add warnings about unsafe MPS settings (Yijing Wang)
    - Simplify interface and messages (Bjorn Helgaas)

  SR-IOV:
    - Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
    - Update NumVFs register when disabling SR-IOV (Yijing Wang)

  Virtualization:
    - Add bus and slot reset support (Alex Williamson)
    - Fix ACS (Access Control Services) issues (Alex Williamson)

  Miscellaneous:
    - Simplify PCIe Capability accessors (Bjorn Helgaas)
    - Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
    - Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
    - Delay enabling bridges until they're needed (Yinghai Lu)
    - Split Designware support into Synopsys and Exynos parts (Jingoo Han)
    - Convert class code to use dev_groups (Greg Kroah-Hartman)
    - Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
    - Fix bridge I/O window alignment (Bjorn Helgaas)
    - Add pci_wait_for_pending_transaction() (Casey Leedom)
    - Use devm_ioremap_resource() in Marvell driver (Tushar Behera)

* tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits)
  PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
  PCI: exynos: Add I/O access wrappers
  PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()
  PCI: Remove pcie_cap_has_devctl()
  PCI: Support PCIe Capability Slot registers only for ports with slots
  PCI: Remove PCIe Capability version checks
  PCI: Allow PCIe Capability link-related register access for switches
  PCI: Add offsets of PCIe capability registers
  PCI: Tidy bitmasks and spacing of PCIe capability definitions
  PCI: Remove obsolete comment reference to pci_pcie_cap2()
  PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment
  PCI: Rename PCIe capability definitions to follow convention
  PCI: Warn if unsafe MPS settings detected
  PCI: Fix MPS peer-to-peer DMA comment syntax
  PCI: Disable decoding for BAR sizing only when it was actually enabled
  PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n
  PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality
  PCI: Don't restrict MPS for slots below Root Ports
  PCI: Simplify MPS test for Downstream Port
  PCI: Remove unnecessary check for pcie_get_mps() failure
  ...
2013-09-03 16:24:35 -07:00
..
asp.c
ccio-dma.c
ccio-rm-dma.c
dino.c
eisa.c
eisa_eeprom.c
eisa_enumerator.c
gsc.c
gsc.h
hppb.c
iommu-helpers.h
iosapic.c parisc: Fix interrupt routing for C8000 serial ports 2013-07-31 23:42:32 +02:00
iosapic_private.h
Kconfig
lasi.c
lba_pci.c PCI: Delay enabling bridges until they're needed 2013-07-25 12:35:03 -06:00
led.c
Makefile
pdc_stable.c
power.c
README.dino
sba_iommu.c
superio.c
wax.c

/*
** HP VISUALIZE Workstation PCI Bus Defect
**
** "HP has discovered a potential system defect that can affect
** the behavior of five models of HP VISUALIZE workstations when
** equipped with third-party or customer-installed PCI I/O expansion
** cards. The defect is limited to the HP C180, C160, C160L, B160L,
** and B132L VISUALIZE workstations, and will only be encountered
** when data is transmitted through PCI I/O expansion cards on the
** PCI bus. HP-supplied graphics cards that utilize the PCI bus are
** not affected."
**
** http://h20000.www2.hp.com/bizsupport/TechSupport/Home.jsp?locale=en_US&prodTypeId=12454&prodSeriesId=44443
**
**	Product		First Good Serial Number
**  C200/C240 (US)	US67350000
**B132L+/B180 (US)	US67390000
**   C200 (Europe)	3713G01000
**  B180L (Europe)	3720G01000
**
** Note that many boards were fixed/replaced under a free replacement
** program. Assume a machine is only "suspect" until proven otherwise.
**
** "The pci_check program will also be available as application
**  patch PHSS_12295"
*/