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RealView boards with certain revisions of the L220 cache controller (ARM11* processors only) may have issues (hardware deadlock) with the recent changes to the mb() barrier implementation (DSB followed by an L2 cache sync). The patch redefines the RealView ARM11MPCore mandatory barriers without the outer_sync() call. Cc: <stable@kernel.org> Tested-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
9 lines
248 B
C
9 lines
248 B
C
/*
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* Barriers redefined for RealView ARM11MPCore platforms with L220 cache
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* controller to work around hardware errata causing the outer_sync()
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* operation to deadlock the system.
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*/
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#define mb() dsb()
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#define rmb() dmb()
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#define wmb() mb()
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