mirror of
https://github.com/torvalds/linux
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3a4347d82e
to use the determine_rate instead of round_rate clk op by default. This caused lots of problems on Rockchip SoCs because they heavily use the composite clk code to model the clk tree. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAmF8sUARHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSVDDhAAn4VSkWRS2mlwSWHCjrNc5XBVqTuzQX4k pH8k8rwLYJgEMnzN0a62I5kPUYcx47ILX/5+64vHfUyxYQsuDWu3O+Uvn8N5q8iD pXwH+Thac30DdCYoi7NRHmfKg0wFuMf4ExlLzfSP64OvPR4OeIz45BLo2KcnASy5 9KW/epH89fwUDpE01p9wI+nS6ItJ3qTvm9PUIOWqUOJz0ZkBjsIid2I6y7k/HgEk sfjBq2swvxaF7cIuCA11vesJ8pFVSSRowHgHdGsHa3okrB/x0nsi2JW2ie2zt/VQ EFkuhuiWfs2O5brjqZiQLgkeggEKkO+9V4o30s3mVFLx9hcEsKR7a3XaPOtXdlHh XrnDKnspWV1HKRRceRMbNw2oxeaDcJ2RC5kXpAVJraGeMDjn1NyYMxCFOyuwY0q6 8Mb7M1dRuMCdjIrhBGss+u5wg/wEG/vUZF6M4LBZAPzgRmX6lKVqzZrLH+9M0xSJ ey77No79nhntzPg57FZHED/ghL+5TNVyp9pO2rDcVcn1QjPGcNw3M9Fm/yfRPAJF C+5mvW5aoc+B6DFuQrpKSfUaa2KgqFKBj2CcEST/fcAH+FNKe9EZ8fkkM0jCdqZo nNK5CbsuW5HSCF+L5EALosru4krAFK/VNzXI7hzfraKOLymkw6h9j78F+Gi0qRzS 0IHipNdFIhA= =5b/O -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fix from Stephen Boyd: "One fix for the composite clk that broke when we changed this clk type to use the determine_rate instead of round_rate clk op by default. This caused lots of problems on Rockchip SoCs because they heavily use the composite clk code to model the clk tree" * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: composite: Also consider .determine_rate for rate + mux composites |
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| .. | ||
| actions | ||
| analogbits | ||
| at91 | ||
| axis | ||
| axs10x | ||
| baikal-t1 | ||
| bcm | ||
| berlin | ||
| davinci | ||
| h8300 | ||
| hisilicon | ||
| imgtec | ||
| imx | ||
| ingenic | ||
| keystone | ||
| loongson1 | ||
| mediatek | ||
| meson | ||
| microchip | ||
| mmp | ||
| mstar | ||
| mvebu | ||
| mxs | ||
| nxp | ||
| pistachio | ||
| pxa | ||
| qcom | ||
| ralink | ||
| renesas | ||
| rockchip | ||
| samsung | ||
| sifive | ||
| socfpga | ||
| spear | ||
| sprd | ||
| st | ||
| sunxi | ||
| sunxi-ng | ||
| tegra | ||
| ti | ||
| uniphier | ||
| ux500 | ||
| versatile | ||
| x86 | ||
| xilinx | ||
| zynq | ||
| zynqmp | ||
| clk-asm9260.c | ||
| clk-aspeed.c | ||
| clk-aspeed.h | ||
| clk-ast2600.c | ||
| clk-axi-clkgen.c | ||
| clk-axm5516.c | ||
| clk-bd718x7.c | ||
| clk-bm1880.c | ||
| clk-bulk.c | ||
| clk-cdce706.c | ||
| clk-cdce925.c | ||
| clk-clps711x.c | ||
| clk-composite.c | ||
| clk-conf.c | ||
| clk-cs2000-cp.c | ||
| clk-devres.c | ||
| clk-divider.c | ||
| clk-fixed-factor.c | ||
| clk-fixed-mmio.c | ||
| clk-fixed-rate.c | ||
| clk-fractional-divider.c | ||
| clk-fractional-divider.h | ||
| clk-fsl-flexspi.c | ||
| clk-fsl-sai.c | ||
| clk-gate.c | ||
| clk-gemini.c | ||
| clk-gpio.c | ||
| clk-hi655x.c | ||
| clk-highbank.c | ||
| clk-hsdk-pll.c | ||
| clk-k210.c | ||
| clk-lmk04832.c | ||
| clk-lochnagar.c | ||
| clk-max9485.c | ||
| clk-max77686.c | ||
| clk-milbeaut.c | ||
| clk-moxart.c | ||
| clk-multiplier.c | ||
| clk-mux.c | ||
| clk-nomadik.c | ||
| clk-npcm7xx.c | ||
| clk-nspire.c | ||
| clk-oxnas.c | ||
| clk-palmas.c | ||
| clk-plldig.c | ||
| clk-pwm.c | ||
| clk-qoriq.c | ||
| clk-rk808.c | ||
| clk-s2mps11.c | ||
| clk-scmi.c | ||
| clk-scpi.c | ||
| clk-si514.c | ||
| clk-si544.c | ||
| clk-si570.c | ||
| clk-si5341.c | ||
| clk-si5351.c | ||
| clk-si5351.h | ||
| clk-sparx5.c | ||
| clk-stm32f4.c | ||
| clk-stm32h7.c | ||
| clk-stm32mp1.c | ||
| clk-twl6040.c | ||
| clk-versaclock5.c | ||
| clk-vt8500.c | ||
| clk-wm831x.c | ||
| clk-xgene.c | ||
| clk.c | ||
| clk.h | ||
| clkdev.c | ||
| Kconfig | ||
| Makefile | ||