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Document Device tree bindings for the quad SPI peripheral found on Microchip PIC32 class devices. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Acked-by: Rob Herring <rob@kernel.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
19 lines
680 B
Plaintext
19 lines
680 B
Plaintext
Microchip PIC32 Quad SPI controller
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-----------------------------------
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Required properties:
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- compatible: Should be "microchip,pic32mzda-sqi".
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- reg: Address and length of SQI controller register space.
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- interrupts: Should contain SQI interrupt.
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- clocks: Should contain phandle of two clocks in sequence, one that drives
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clock on SPI bus and other that drives SQI controller.
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- clock-names: Should be "spi_ck" and "reg_ck" in order.
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Example:
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sqi1: spi@1f8e2000 {
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compatible = "microchip,pic32mzda-sqi";
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reg = <0x1f8e2000 0x200>;
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clocks = <&rootclk REF2CLK>, <&rootclk PB5CLK>;
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clock-names = "spi_ck", "reg_ck";
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interrupts = <169 IRQ_TYPE_LEVEL_HIGH>;
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};
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