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7af5b901e8
With LPAE enabled, privileged no-access cannot be enforced using CPU domains as such feature is not available. This patch implements PAN by disabling TTBR0 page table walks while in kernel mode. The ARM architecture allows page table walks to be split between TTBR0 and TTBR1. With LPAE enabled, the split is defined by a combination of TTBCR T0SZ and T1SZ bits. Currently, an LPAE-enabled kernel uses TTBR0 for user addresses and TTBR1 for kernel addresses with the VMSPLIT_2G and VMSPLIT_3G configurations. The main advantage for the 3:1 split is that TTBR1 is reduced to 2 levels, so potentially faster TLB refill (though usually the first level entries are already cached in the TLB). The PAN support on LPAE-enabled kernels uses TTBR0 when running in user space or in kernel space during user access routines (TTBCR T0SZ and T1SZ are both 0). When running user accesses are disabled in kernel mode, TTBR0 page table walks are disabled by setting TTBCR.EPD0. TTBR1 is used for kernel accesses (including loadable modules; anything covered by swapper_pg_dir) by reducing the TTBCR.T0SZ to the minimum (2^(32-7) = 32MB). To avoid user accesses potentially hitting stale TLB entries, the ASID is switched to 0 (reserved) by setting TTBCR.A1 and using the ASID value in TTBR1. The difference from a non-PAN kernel is that with the 3:1 memory split, TTBR1 always uses 3 levels of page tables. As part of the change we are using preprocessor elif definied() clauses so balance these clauses by converting relevant precedingt ifdef clauses to if defined() clauses. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reviewed-by: Kees Cook <keescook@chromium.org> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
102 lines
1.9 KiB
ArmAsm
102 lines
1.9 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* linux/arch/arm/lib/csumpartialcopyuser.S
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*
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* Copyright (C) 1995-1998 Russell King
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*
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* 27/03/03 Ian Molton Clean up CONFIG_CPU
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/errno.h>
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#include <asm/asm-offsets.h>
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.text
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#if defined(CONFIG_CPU_SW_DOMAIN_PAN)
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.macro save_regs
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mrc p15, 0, ip, c3, c0, 0
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stmfd sp!, {r1, r2, r4 - r8, ip, lr}
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uaccess_enable ip
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.endm
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.macro load_regs
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ldmfd sp!, {r1, r2, r4 - r8, ip, lr}
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mcr p15, 0, ip, c3, c0, 0
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ret lr
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.endm
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#elif defined(CONFIG_CPU_TTBR0_PAN)
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.macro save_regs
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mrc p15, 0, ip, c2, c0, 2 @ read TTBCR
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stmfd sp!, {r1, r2, r4 - r8, ip, lr}
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uaccess_enable ip
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.endm
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.macro load_regs
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ldmfd sp!, {r1, r2, r4 - r8, ip, lr}
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mcr p15, 0, ip, c2, c0, 2 @ restore TTBCR
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ret lr
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.endm
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#else
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.macro save_regs
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stmfd sp!, {r1, r2, r4 - r8, lr}
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.endm
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.macro load_regs
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ldmfd sp!, {r1, r2, r4 - r8, pc}
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.endm
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#endif
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.macro load1b, reg1
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ldrusr \reg1, r0, 1
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.endm
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.macro load2b, reg1, reg2
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ldrusr \reg1, r0, 1
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ldrusr \reg2, r0, 1
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.endm
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.macro load1l, reg1
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ldrusr \reg1, r0, 4
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.endm
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.macro load2l, reg1, reg2
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ldrusr \reg1, r0, 4
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ldrusr \reg2, r0, 4
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.endm
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.macro load4l, reg1, reg2, reg3, reg4
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ldrusr \reg1, r0, 4
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ldrusr \reg2, r0, 4
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ldrusr \reg3, r0, 4
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ldrusr \reg4, r0, 4
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.endm
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/*
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* unsigned int
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* csum_partial_copy_from_user(const char *src, char *dst, int len)
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* r0 = src, r1 = dst, r2 = len
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* Returns : r0 = checksum or 0
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*/
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#define FN_ENTRY ENTRY(csum_partial_copy_from_user)
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#define FN_EXIT ENDPROC(csum_partial_copy_from_user)
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#include "csumpartialcopygeneric.S"
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/*
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* We report fault by returning 0 csum - impossible in normal case, since
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* we start with 0xffffffff for initial sum.
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*/
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.pushsection .text.fixup,"ax"
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.align 4
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9001: mov r0, #0
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load_regs
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.popsection
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