linux/drivers/clocksource/sunxi_timer.c
Linus Torvalds b274776c54 arm-soc: cleanups
A large number of cleanups, all over the platforms. This is dominated
 largely by the Samsung platforms (s3c, s5p, exynos) and a few of the
 others moving code out of arch/arm into more appropriate subsystems.
 The clocksource and irqchip drivers are now abstracted to the point
 where platforms that are already cleaned up do not need to even specify
 the driver they use, it can all get configured from the device tree
 as we do for normal device drivers. The clocksource changes basically
 touch every single platform in the process.
 
 We further clean up the use of platform specific header files here,
 with the goal of turning more of the platforms over to being
 "multiplatform" enabled, which implies that they cannot expose
 their headers to architecture independent code any more.
 
 It is expected that no functional changes are part of the cleanup.
 The overall reduction in total code lines is mostly the result of
 removing broken and obsolete code.
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Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Arnd Bergmann:
 "A large number of cleanups, all over the platforms.  This is dominated
  largely by the Samsung platforms (s3c, s5p, exynos) and a few of the
  others moving code out of arch/arm into more appropriate subsystems.

  The clocksource and irqchip drivers are now abstracted to the point
  where platforms that are already cleaned up do not need to even
  specify the driver they use, it can all get configured from the device
  tree as we do for normal device drivers.  The clocksource changes
  basically touch every single platform in the process.

  We further clean up the use of platform specific header files here,
  with the goal of turning more of the platforms over to being
  "multiplatform" enabled, which implies that they cannot expose their
  headers to architecture independent code any more.

  It is expected that no functional changes are part of the cleanup.
  The overall reduction in total code lines is mostly the result of
  removing broken and obsolete code."

* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (133 commits)
  ARM: mvebu: correct gated clock documentation
  ARM: kirkwood: add missing include for nsa310
  ARM: exynos: move exynos4210-combiner to drivers/irqchip
  mfd: db8500-prcmu: update resource passing
  drivers/db8500-cpufreq: delete dangling include
  ARM: at91: remove NEOCORE 926 board
  sunxi: Cleanup the reset code and add meaningful registers defines
  ARM: S3C24XX: header mach/regs-mem.h local
  ARM: S3C24XX: header mach/regs-power.h local
  ARM: S3C24XX: header mach/regs-s3c2412-mem.h local
  ARM: S3C24XX: Remove plat-s3c24xx directory in arch/arm/
  ARM: S3C24XX: transform s3c2443 subirqs into new structure
  ARM: S3C24XX: modify s3c2443 irq init to initialize all irqs
  ARM: S3C24XX: move s3c2443 irq code to irq.c
  ARM: S3C24XX: transform s3c2416 irqs into new structure
  ARM: S3C24XX: modify s3c2416 irq init to initialize all irqs
  ARM: S3C24XX: move s3c2416 irq init to common irq code
  ARM: S3C24XX: Modify s3c_irq_wake to use the hwirq property
  ARM: S3C24XX: Move irq syscore-ops to irq-pm
  clocksource: always define CLOCKSOURCE_OF_DECLARE
  ...
2013-02-21 14:58:40 -08:00

161 lines
3.9 KiB
C

/*
* Allwinner A1X SoCs timer handling.
*
* Copyright (C) 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* Based on code from
* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
* Benn Huang <benn@allwinnertech.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/sunxi_timer.h>
#include <linux/clk-provider.h>
#define TIMER_CTL_REG 0x00
#define TIMER_CTL_ENABLE (1 << 0)
#define TIMER_IRQ_ST_REG 0x04
#define TIMER0_CTL_REG 0x10
#define TIMER0_CTL_ENABLE (1 << 0)
#define TIMER0_CTL_AUTORELOAD (1 << 1)
#define TIMER0_CTL_ONESHOT (1 << 7)
#define TIMER0_INTVAL_REG 0x14
#define TIMER0_CNTVAL_REG 0x18
#define TIMER_SCAL 16
static void __iomem *timer_base;
static void sunxi_clkevt_mode(enum clock_event_mode mode,
struct clock_event_device *clk)
{
u32 u = readl(timer_base + TIMER0_CTL_REG);
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
u &= ~(TIMER0_CTL_ONESHOT);
writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
break;
case CLOCK_EVT_MODE_ONESHOT:
writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
default:
writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
break;
}
}
static int sunxi_clkevt_next_event(unsigned long evt,
struct clock_event_device *unused)
{
u32 u = readl(timer_base + TIMER0_CTL_REG);
writel(evt, timer_base + TIMER0_CNTVAL_REG);
writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
timer_base + TIMER0_CTL_REG);
return 0;
}
static struct clock_event_device sunxi_clockevent = {
.name = "sunxi_tick",
.rating = 300,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = sunxi_clkevt_mode,
.set_next_event = sunxi_clkevt_next_event,
};
static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = (struct clock_event_device *)dev_id;
writel(0x1, timer_base + TIMER_IRQ_ST_REG);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction sunxi_timer_irq = {
.name = "sunxi_timer0",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
.handler = sunxi_timer_interrupt,
.dev_id = &sunxi_clockevent,
};
static struct of_device_id sunxi_timer_dt_ids[] = {
{ .compatible = "allwinner,sunxi-timer" },
{ }
};
void __init sunxi_timer_init(void)
{
struct device_node *node;
unsigned long rate = 0;
struct clk *clk;
int ret, irq;
u32 val;
node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
if (!node)
panic("No sunxi timer node");
timer_base = of_iomap(node, 0);
if (!timer_base)
panic("Can't map registers");
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0)
panic("Can't parse IRQ");
of_clk_init(NULL);
clk = of_clk_get(node, 0);
if (IS_ERR(clk))
panic("Can't get timer clock");
rate = clk_get_rate(clk);
writel(rate / (TIMER_SCAL * HZ),
timer_base + TIMER0_INTVAL_REG);
/* set clock source to HOSC, 16 pre-division */
val = readl(timer_base + TIMER0_CTL_REG);
val &= ~(0x07 << 4);
val &= ~(0x03 << 2);
val |= (4 << 4) | (1 << 2);
writel(val, timer_base + TIMER0_CTL_REG);
/* set mode to auto reload */
val = readl(timer_base + TIMER0_CTL_REG);
writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
ret = setup_irq(irq, &sunxi_timer_irq);
if (ret)
pr_warn("failed to setup irq %d\n", irq);
/* Enable timer0 interrupt */
val = readl(timer_base + TIMER_CTL_REG);
writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
sunxi_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
0x1, 0xff);
}