linux/arch/mn10300/mm
Mark Salter 5a226c6f5c MN10300: Map userspace atomic op regs as a vmalloc page
The AM34 processor has an atomic operation that's the equivalent of LL/SC on
other architectures.  However, rather than being done through a pair of
instructions, it's driven by writing to a pair of memory-mapped CPU control
registers.

One set of these registers (AARU/ADRU/ASRU) is available for use by userspace,
but for userspace to access them a PTE must be set up to cover the region.
This is done by dedicating the first vmalloc region page to this purpose,
setting the permissions on its PTE such that userspace can access the page.

glibc is hardcoded to expect the registers to be there.

The way atomic ops are done through these registers is straightforward:

 (1) Write the address of the word you wish to access into AARU.  This causes
     the CPU to go and fetch that word and load it into ADRU.  The status bits
     are also cleared in ASRU.

 (2) The current data value is read from the ADRU register and modified.

 (3) To alter the data in RAM, the revised data is written back to the ADRU
     register, which causes the CPU to attempt to write it back.

 (4) The ASRU.RW flag (ASRU read watch), ASRU.LW flag (bus lock watch),
     ASRU.IW (interrupt watch) and the ASRU.BW (bus error watch) flags then
     must be checked to confirm that the operation wasn't aborted.  If any of
     the watches have been set to true, the operation was aborted.

Signed-off-by: Mark Salter <msalter@redhat.com>
Signed-off-by: David Howells <dhowells@redhat.com>
2010-10-27 17:28:56 +01:00
..
cache-disabled.c MN10300: Handle missing sys_cacheflush() when caching disabled 2010-09-28 18:01:14 -07:00
cache-flush-by-reg.S MN10300: AM34: Add cacheflushing by using the AM34 purge registers 2010-10-27 17:28:45 +01:00
cache-flush-by-tag.S MN10300: SMP: Differentiate local cache flushing 2010-10-27 17:28:45 +01:00
cache-flush-icache.c MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
cache-inv-by-reg.S MN10300: AM34: Add cacheflushing by using the AM34 purge registers 2010-10-27 17:28:45 +01:00
cache-inv-by-tag.S MN10300: SMP: Differentiate local cache flushing 2010-10-27 17:28:45 +01:00
cache-inv-icache.c MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
cache-smp-flush.c MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
cache-smp-inv.c MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
cache-smp.c MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
cache-smp.h MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
cache.c MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
dma-alloc.c arch/mn10300/mm: eliminate NULL dereference 2010-08-23 11:41:24 -07:00
extable.c
fault.c MN10300: And Panasonic AM34 subarch and implement SMP 2010-10-27 17:28:55 +01:00
init.c MN10300: Map userspace atomic op regs as a vmalloc page 2010-10-27 17:28:56 +01:00
Kconfig.cache MN10300: Cache: Implement SMP global cache flushing 2010-10-27 17:28:47 +01:00
Makefile MN10300: SMP TLB flushing 2010-10-27 17:28:51 +01:00
misalignment.c MN10300: BUG to BUG_ON changes 2010-10-27 17:28:33 +01:00
mmu-context.c MN10300: Make the use of PIDR to mark TLB entries controllable 2010-10-27 17:28:49 +01:00
pgtable.c MN10300: Rename __flush_tlb*() to local_flush_tlb*() 2010-10-27 17:28:49 +01:00
tlb-mn10300.S MN10300: Use the [ID]PTEL2 registers rather than [ID]PTEL for TLB control 2010-10-27 17:28:50 +01:00
tlb-smp.c MN10300: SMP TLB flushing 2010-10-27 17:28:51 +01:00